Functional Description

The APB3 to AXI4 Lite Converter core includes an error detection feature. In the case of timeout (128 clock cycles), that is the AXI4-Lite interface is not responding, the APB3 slave interface asserts the s_apb3_pslverror signal high.

Note: Efinix® recommends that you set the delay clock cycle not more than 123 when using wait write or wait read operation. This allows at least five clock cycles for the write or read operation to complete before reaching the timeout.
  • APB3 Slave interface—Provides a bidirectional slave interface to the core. The APB3 data bus widths are always fixed at 32 bits, while address width can vary from 2 to 32 bits. The APB3 interface performs write transfers when the s_apb3_pwrite signal is high and read transfers when the s_apb3_pwrite signal is low.
  • AXI4 Master Interface—Provides the AXI4-lite master interface to the core. The data bus widths are fixed at 32 bits, while the address is equal to the APB3 address width.
Figure 1. APB3 to AXI4 Lite Converter System Block Diagram