Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.
Table 2. Titanium Resource Utilization and Performance
FPGA Address Width (bit) Logic/ Adders Flipflops Memory Blocks DSP48 Blocks fMAX (MHz)1 Efinity® Version2
Ti60 F225 C4 10 29 100 0 0 656 2021.2
16 30 112 0 0 578
32 29 144 0 0 580
Table 3. Trion Resource Utilization and Performance
FPGA Address Width (bit) Logic Utilization (LUTs) Registers Memory Blocks Multipliers fMAX (MHz)1 Efinity® Version2
T20 BGA256 C4 10 36 100 0 0 265 2021.1
16 36 112 0 0 289
32 36 144 0 0 289
1 Using default parameter settings.
2 Using Verilog HDL.