APB3 to AXI4 Lite Converter Operations

Assert the s_apb3_penable one clock cycle after asserting s_apb3_psel and s_apb3_pwrite to start the write operation. The write operation is complete when the s_apb3_pready toggles to high then low, five cycles after s_apb3_psel and s_apb3_pwrite go high.

Figure 1. Write Operation Waveform (ADDR_WTH = 10)

Assert the s_apb3_penable one clock cycle after asserting s_apb3_psel and s_apb3_pwrite to start the wait write operation. Then, assert the m_axi_awready and m_axi_wready signals after the number of wait delay cycles. The write operation is complete when the s_apb3_pready toggles to high then low, five plus the wait delay cycles after s_apb3_psel and s_apb3_pwrite go high.

Figure 2. Wait Write Operation Waveform (ADDR_WTH = 10, wait 5 clock cycle)

Assert the s_apb3_penable one clock cycle after asserting s_apb3_psel to start the read operation. The read operation is complete when the s_apb3_pready toggles to high then low, four cycles after s_apb3_psel goes high.

Figure 3. Read Operation Waveform (ADDR_WTH = 10)

Assert the s_apb3_penable one clock cycle after asserting s_apb3_psel to start the read operation. Then, assert the m_axi_arready signal after the number of wait delay cycles. The read operation is complete when the s_apb3_pready toggles to high then low, four plus the wait delay cycles after s_apb3_psel goes high.

Figure 4. Read Write Operation Waveform (ADDR_WTH = 10, wait 5 clock cycle)