Every computer relies on some processor element to capture, move, and manipulate digital data, and the basic instructions used to build all higher-level functions comprise an instruction set architecture (ISAs). Hardware implementations of ISAs have always been proprietary IP of semiconductor vendors with some implementations (most notably ARM) available through license. Now the open-source community has taken up a new ISA, known as RISC-V, which is based on reduced instruction set computing principles.

RISC-V logo

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Unlike most other ISA designs, it is made available under an open-source license that does not require any formal license from a semiconductor vendor. The standard has several levels of instruction sets, including 32-bit and 64-bit varieties, and vendors are even licensing soft cores that can run in a variety of hardware implementations. With access to an open-source implementation, innovative developers can build on top of a proven platform and quickly innovate new products.

FPGAs already offer several benefits at all stages of product development, both as prototyping tools and as a system’s primary compute element. Today, RISC-V implementations are now possible with soft cores available as IP from FPGA vendors, and the industry has moved quickly to embrace this open-source standard. Now it’s never been easier to start building RISC-V implementations that are specialized for advanced applications.

What is RISC-V?

The RISC-V architecture was originally developed by a group of researchers at the Parallel Computing Laboratory (Par Lab) at UC Berkeley under public and private funding agreements. Prior versions of RISC (I-IV) had been developed since 1981. The first hardware implementation was built on 28 nm FD-SOI in 2011 to illustrate the benefits of such an open architecture. The RISC-V foundation would later be founded with 36 member organizations and the specification was put into the public domain under a Creative Commons license. Today, the RISC-V source is managed as an open-source software project.

Since its inception, interest in RISC-V-based implementations has continued to grow among industry and academia. The specification is attractive because it is a free and open standard to which software can be ported, and anyone can develop their own compatible hardware platforms. This is in contrast to x86 or ARM implementations, which must be licensed from vendors in order to access the IP required to build an implementation and take a product to market. The RISC-V standard opens the door to innovators who might otherwise not have the resources to build their own ISA or license a vendor’s ISA.

Technical Capabilities

The RISC-V standard offers an important group of technical capabilities that set it apart from proprietary ISAs. The specification is built to be used either as a standalone implementation, or extended to specific applications with additional instructions that a developer wants to instantiate.

  • Modularity - The RISC-V specification was built to have a modular architecture. The specification includes a set of base instructions and optional extensions. The ISA extensions can be enabled or disabled as needed.
  • Memory - Officially, the RISC-V instruction set can support 32, 64, and 128-bit word widths. However, the 128-bit width remains undefined due to the lack of industry experience in implementing system architectures that can support such large word widths.
  • Extensibility - The base specification and standard extensions can be used immediately in a hardware implementation alongside peripherals in a new chip design to build a simple computer. However, it is also extensible into a proprietary implementation from the base specification by adding a set of user-defined extensions.
  • Acceleration - The optimized instruction set in RISC-V reduces compute overhead when deployed on a power optimized hardware platform, particularly on an FPGA. Developers can maximize compute density and minimize power consumption through an optimized RISC-V implementation.

With these capabilities available as open-source development libraries and software, developers can more quickly bring a new product to market with more control over the operation of their hardware.

Why Use RISC-V Cores?

Clearly, there are multiple advantages from the perspective of hardware capabilities, as well as for application developers. Hardware implementations of RISC-V can be highly application-specific chipsets because the implementation is not mandated at the ISA level.

Open-source - The first and most obvious reason to use a RISC-V-based implementation is the fact that the standard is open-source. There is no license fee required to access the ISA and begin using it to develop new products. This translates into faster time to market and reduced development effort, as well as the ability to build a totally custom standard and create a new business model around core IP based on an open instruction set.

Community guidance - Whenever an open-source project becomes successful, a thriving community starts to grow around the project. RISC-V is no different, and now a community of RISC-V developers can be leveraged for development advice, open-source implementation projects, and new versions of the standard. The level of community support for RISC-V is still growing, but vendor IP based on the RISC-V standard is also emerging to fill in the gaps.

RISC-V vs. ARM - The ARM architecture is proprietary and requires a license to use when building a processor. ARM developers can only use the ARM ISA to build a new processor without customization, although this is changing. Hardware developers can do much more with RISC-V; they can develop extensions on top of RISC-V that extends its capabilities beyond the core instruction set. Vendors could even develop their own proprietary version of RISC-V, where the open ISA is still used but the vendor IP is still available for license.

While the main advantages of RISC-V surround the business model for embedded systems development, there are technical reasons to move to RISC-V-based systems. Developers can build on top of the base specification and implement precisely the instruction groups needed for their application without having to pay for unused chip area. Applications like IoT, mobile, edge computing, wearables, vision systems, and sensor fusion often require some optimization and tradeoffs between power consumption and compute density.

In addition to these high-level points, application developers

  • The RISC-V architecture helps reduce overhead that is responsible for power-inefficient computation in high compute applications.
  • Customizability of the specification allows a product to be built to high specificity, yet it is still possible the custom extensions can be made interoperable with custom logic.
  • Aspects like security in RISC-V are comparable to those measures implemented in ARM and x86.
  • RISC-V developers can optimize performance by combining applications that use standard and custom ISA extensions.

Applications that require high specificity on customized hardware platforms may be best built using a RISC-V implementation. Similarly, if a company wants to develop their own IP without starting from scratch, the RISC-V architecture provides a solid foundation for building a portfolio of proprietary development resources that eventually form a complete product line.

Due to the significant advantages of the RISC-V architecture, prominent semiconductor manufacturers are now releasing their own RISC-V compatible products that take advantage of the standard’s open ISA. This move towards supporting a popular open-source framework helps spur innovation and broadens the potential developer base for new embedded products. Less reliance on proprietary ISAs means companies can also develop their own RISC-V variants that differentiate products.

Getting Started With RISC-V Development

With RISC-V being open source, anyone can download the original source code from the risc-v.org website or from GitHub. Users can then build a RISC-V implementation using vendor development tools, typically by starting from a reference design. Thanks to semiconductor vendor support for RISC-V-based implementations and multiple open-source options,

  1. Find a known working reference design that offers the desired feature set or application acceleration.
  2. Purchase vendor development products and begin customizing the design to meet application need.
  3. Start with an open-source core that can be freely downloaded and used as-is.

Paths #1 and #2 would normally require a license from a semiconductor vendor, and part #3 was practically non-existent before RISC-V. The use of RISC-V makes #3 a viable option for developers that want to build custom processors for highly specific compute tasks.

The path to market can be reduced even further through implementation on an FPGA. The merging of open-source or vendor provided core designs with FPGA development is a perfect path for developing custom hardware, but without the manufacturing costs and complexities that come with building a custom ASIC. For smaller fabless companies that want to produce new products at scale, FPGAs are the ideal choice.

Edge Computing

Using RISC-V with FPGAs

If you have decided to take advantage of an FPGA platform to build your embedded system, consider using a RISC-V architecture for the implementation. FPGAs and RISC-V together offer extensive control over the system architecture and its core functions in the instruction set, something which would be difficult in other ISAs or when developing all FPGA logic from scratch.

Why FPGAs?

FPGAs offer multiple benefits generally, regardless of the ISA implemented in silicon. FPGA platforms offer high I/O count and bandwidth that is needed in advanced embedded computing applications, but with the ability to instantiate additional user functions at the hardware level. The major benefits center around customization and reconfigurability of FPGAs, ranging from the high-level application down to the hardware level. Devices that would normally require a broad chipset or a specialized SoC can benefit by instantiating core functions on an FPGA:

Optimized hardware - Unlike an MCU/MPU, FPGAs can be developed to include only the required interfaces and peripherals that are needed in a particular application. The component can be reconfigured later as needed so that the architecture can be continuously optimized.

Security - As is the case in any advanced computing system, security is a major concern and the system’s primary chipset should prevent exposure of sensitive data. FPGAs provide superior security in terms of limiting physical access as well as security features in the ISA implementation.

Supply chain - Developers will see lower supply chain risk associated with FPGAs. Products from the same vendor are generally interchangeable without additional development work, and peripherals can be built into the main FPGA system controller. Both aspects eliminate the need for external parts or variant designs.

Application Areas Supported by RISC-V

The ideal application areas for RISC-V based FPGA implementations involve data aggregation, low-latency processing, operations on diverse data streams (interfaces), and low power implementations. Some example application areas are summarized below.

Application Characteristics
Embedded AI This is probably the most popular application area where RISC-V is implemented. Running AI in an embedded system requires very low latency and power consumption, and the recent trend has been to use accelerator chips to implement this use case. Using RISC-V allows a developer to optimize a softcore for their FPGA so that component count can be reduced, and so that users can optimize compute vs. power.
Sensor fusion FPGA usage in sensor fusion arises due to the number of I/Os typically available with these processors, allowing multiple data streams to be aggregated and processed. A developer can customize a RISC-V core to optimize compute for specific sensor groups, as well as implement custom interfaces that might typically require an external component.
Robotics Modern robotics requires real-time processing based on data from multiple sources, similar to sensor fusion.
Defense and security Defense systems already make use of FPGAs to implement reconfigurable, interoperable systems with high compute requirements. Use cases like autonomous defense systems, future-proofed interoperability, modernization, sensing and signal processing, vision, and much more are all essential in defense systems. RSIC-V can be used in an FPGA to optimize the hardware architecture specifically for these applications.
Vision This extension of sensor fusion involves aggregation of multiple data streams, and possibly some processing implemented on data streams as they arrive. A RSIC-V implementation on an FPGA for these tasks offers an opportunity to eliminate any unused functions and tailor processing algorithms in a single component. The result is reduced power consumption and lower latency than an alternative chipset or system architecture.

In many of these areas, the FPGA is playing the role of an accelerator, as a system controller, or a mix of these roles. RISC-V implementations on an FPGA make excellent application-specific accelerators due to the ability to select extensions for a specific implementation. Further addition of standard and user-defined extensions allow an SoC to be built that can act as the main host controller and accelerator in the same package.

Development Process With RISC-V-based FPGAs

With the major FPGA vendors supporting RISC-V implementations on their products, developers can port RISC-V processor IP onto an FPGA using vendor development tools. This follows a similar process as would be used to instantiate any other IP block in an FPGA. Users access the core IP, add their own code in C to build an application, and compile everything to a bitstream. The resulting bin/hex file is flashed into system memory.

  1. Access source code for the RISC-V core, either from vendor IP or from an open-source repository.
  2. Imported the RISC-V core into the vendor IDE and customize if needed to support the particular application.
  3. Develop the embedded application written in C and compile for the RISC-V core using readily available open-source tools.
  4. Download the compiled application to the configured FPGA for the RISC-V core to run.

Vendor tools and an open-source code editor like Eclipse are recommended for compiling code into a RISC-V core for implementation on an FPGA. Vendors should be able to support custom implementations as well, either starting from vendor IP or modified from an open-source implementation.

Physical Design and Layout

Once the application development portion is complete, the FPGA can be placed on a PCB and packaged just like any other component. The board form factor and system integration option will depend on the end application area. The table below outlines some options for FPGA integration options for some advanced embedded applications.

Single PCB Expansion Card System-on-Module
AI accelerator
Sensor fusion platforms
Edge computing
IoT and mobile
High-bandwidth video processing
Modular hardware platforms
5G and telecom

Designers can implement the FPGA in these form factors as a standalone processor, as an accelerator in part of a larger chipset, or even as a co-processor with a conventional MCU/MPU/SoC available from another vendor. FPGAs offer flexibility in how they are implemented and used alongside other chips, and they give developers the ability to expand a system’s capabilities beyond what is available in conventional processors and ASICs. Make sure you choose an FPGA vendor that can meet your IP requirements and that has ready-to-deploy RISC-V core implementations.

RISC-V SoC Implementation With Efinix

As more semiconductor vendors have jumped into RISC-V development and implementation, it is natural we start to see the same from FPGA vendors. Efinix is at the forefront of FPGA vendors targeting a range of applications that can benefit from the acceleration provided by RISC-V implementations. These application areas include embedded AI, edge computing, wearables, IoT, sensor fusion, and machine vision.

Product Lines

Efinix’s two FPGA product lines can support RISC-V implementations that target high compute density applications. The Titanium and Trion FPGA lines target a range of logic cell requirements with high compute density and multiple interfaces for advanced applications. Multiple part numbers are available with various package sizes and interfaces included on the device.

Titanium FPGAs

Titanium Logo

A larger FPGA solution for more advanced applications requiring more logic capacity and I/O count. These devices are built on a similar architecture as Trion products with broader support for standard data/memory interfaces, as well as SerDes interfaces with high data rate.

  • Up to 1M logic cells
  • 4-lane MIPI, DDR4/LPDDR4, up to 25.8 Gbps SerDes, PCIe Gen4 interfaces supported
  • DSP block optimized for high compute applications like AI
  • Efinix RISC-V core with integrated audio and vision interfaces
  • Ideal for high compute industrial systems, larger vision products, and edge AI applications

The Titanium FPGA offers larger logic cell count and additional interfaces, offering greater feature density than the smaller Trion products. This makes the Titanium a better fit for an RISC-V SoC implementation, where the device can act as a main system controller with integrated peripherals.

Trion® FPGAs

Trion Logo

A smaller FPGA option for embedded systems, these components take up small amounts of board space yet provide access to high I/O count and high logic cell count. These devices include standard integrated interfaces and will support additional high speed interfaces required in high compute applications::

  • Up to 120k logic cells
  • 4-lane MIPI, LVDS, and up to DDR3/LPDDR3 interfaces supported
  • Dedicated interface block
  • Efinix RISC-V core with integrated audio and vision processing
  • Ideal for mobile/IoT products, smaller vision products, and AI inference applications

RISC-V-based systems deployed on a Trion FPGA platform offer acceleration needed to optimize smaller devices for high compute with low power consumption. The IP and development libraries available from Efinix allow the Trion FPGA to be used as a standalone processor, or as a dedicated application-specific compute element or accelerator.

Resources for RISC-V Developers

To help customers quickly adopt a RISC-V implementation in their embedded systems, Efinix created a RISC-V SoC based on the open-source VexRiscv core. The main features in this development library include:

  • 32-bit CPU using the RISCV32I ISA with M, A, F, D, and C extensions, and pipeline stages
  • Library includes a configurable feature set with user peripherals (SPI, I2C, etc.) on an APB bus
  • RISC-V processor, memory, multiple high-speed I/Os, customizable interfaces, and memory controllers on an AXI bus
  • Efinix provides two variants of its standard RISC-V SoC library: Sapphire and Edge Vision. This RISC-V SoC libraries from Efinix provide a highly integrated SoC that is optimized for power consumption and compute density. The development tools and libraries provided by Efinix enable the customizability developers expect in an industry-leading FPGA platform.

    Sapphire SoC - This use -configurable, high-performance SoC includes 6 pipeline stages (fetch, injector, decode, execute, memory, and write back) with an optional memory controller (DDR or HyperRAM up to 3.5 GB), all running at high clock frequency. Support for standard and custom features can be integrated and managed in Efinix development tools. There is also extensive access to peripherals with multiple interfaces (up to 32 GPIOs, 3 I2C masters, 3 SPI masters, and 3 UARTs).

    Edge Vision SoC - This SoC library extends the Sapphire SoC to target vision applications, with all buses, controllers, and interfaces included in the development library. Additional user functions and instantiation of specialized processing blocks can also be implemented at a system level as well as RISC-V acceleration at the instruction level. The goal of this accelerator implementation is to facilitate hardware/software partitioning with specific functions applied to streaming vision data, all operating at low latency.

    FPGA developers can accelerate innovation cycles and the path to market with developer resources supporting advanced application areas. To help FPGA designers start developing with Titanium or Trion FPGAs, Efinix offers a developer environment to implement user functions within a RISC-V framework.

    Efinity IDE - The Efinity IDE is Efinix’s development environment for Titanium and Trion FPGAs. Efinity provides a complete environment for developing RISC-V implementations for Efinix FPGAs, including standard and user-defined extensions. With access to the Sapphire and Edge Vision SoC libraries, users can design their RISC-V based implementation in the Efinity GUI or with built-in command-line scripting support. Some of the major development features of the Efinix IDE include:

  • Project management dashboard
  • Interface and floorplan design tool for logic design, pin assignment, and routing
  • Timing analysis features to analyze and optimize device performance
  • Hardware debuggers for logic analysis
  • Simulation support with ModelSim, NCSim, and iVerilog simulators
  • 1-year licenses are available to customers who purchase a development kit. The license includes one year of upgrades and a free maintenance renewal is available upon request.

    The Efinity IDE uses a simple process and interface to configure RISC-V cores for Trion and Titanium FPGAs:

    1. Configure the soft RISC-V core directly from the Efinity IP Manager. Use the IDE to configure the size of the core, its peripherals, memory footprint, and any other built-in features.
    2. Hit “Create” and the core is dropped into your FPGA design. When the design is compiled to a bitstream, the RISC-V core is instantiated automatically. The open-source Eclipse toolset is recommended for writing and compiling C code for the RISC-V core.
    3. Download the compiled hex file to the system memory and the RISC-V core will run the embedded application as expected.

    Why Efinix?

    Efinix has partnered with a broad range of customers and focuses its product lines on applications requiring high compute in small form factor devices. Its customers are innovative industrial, consumer, medical device manufacturers, or high-end automotive companies. Ideal applications include vision, sensor fusion, and on-device AI/ML in these markets. The low power consumption and small footprint of Efinix’s flagship products make them perfect for surveillance or industrial automation applications.

    Efinix customers tend to require a tailored small form-factor FPGA solution that helps eliminate significant R&D costs while still allowing product customization and reconfiguration. The RISC-V and Edge Vision SoC libraries are instrumental for Efinix customers as they help expedite creation of new designs and reduce time to market.

    Developers that want a faster path to market with an alternative option to larger FPGA platforms can leverage the significant developer resources and powerful compute capabilities provided by Efinix FPGAs. As a smaller company, Efinix takes a high-touch approach that leads to longer-term relationships and innovative FPGA applications.

    Get Started with Efinix

    To get started with Efinix FPGAs, take a look at our development kits and developer resources.