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August 12, 2026
Design partitions streamline the creation of large, complex FPGA floorplans by separating the design space into defined bounding boxes. Each partition is named and assigned to a specific area in the device floorplan. Partitions not only ensure the quality and reproducibility of logic placement, routing, and timing results across design iterations, but also enforce floorplanning requirements with placement constraints.
Partitions accelerate design flows for both individual developers and development teams through their modularity. Developers can work in sequence or parallel, choosing to implement different partitions at different stages of the design.
Additionally, partition- and preservation-based workflows reduce compilation times across all stages of the development process:
Distributed compilation workload—the bulk of the compilation work is done for individual partitions in separate development environments.
Smaller compilations—parts of the design are compiled separately, so the compilation contexts are more compact than the total design.
Preserved placing and routing—when integrating all design partitions in a final compilation, the cells and routes from imported partitions are preserved.
Partitions support a variety of innovative workflows:
Design re-use—reuse partitions across projects and designs through a bottom-up preservation flow.
Incremental compilation—reduce compile times across project and design iterations by reusing compilation results.
Team-based design—reduce overall development time with multiple users developing distinct parts of the design in parallel.
In the incremental compilation and core reuse workflows, importing and exporting partitions between project segments allows for iterative, modular design.
The following diagram shows how different partitions are implemented at each project stage of a larger design:
Choose mixed preservation flows for each optimal use case:
Incremental compilation—locks down the netlist, placement, and routing for parts of a design, while allowing for further iteration on the unlocked portion.
Core re-use—migrates the preserved portion of the design to a new project, which can then be used for a new iteration of the project or for entirely different designs.
The team-based design methodology enables chip design collaboration and concurrent development among individual developers or larger teams. Partitions are defined to serve distinct purposes within the larger design. The partitions are then assigned to different developers or teams, who can work in parallel without competing over device resources.
Once all partitions are completed, an integration compile brings them together into the final design. Adjustment and iteration take place at all stages of the process.
The following diagram illustrates the team-based design workflow:
Efinix recognizes the advantages of partition-based workflows. The Efinity software version 2026.1 allows you to create and use partitions in the Partition Planner. Use the Partition Planner when creating designs for Titanium family and Topaz family FPGAs.
Open the Partition Planner in the Efinity GUI after opening an active project.
The Partition Planner has the following windows:
Partition Assignments—Shows the partitions in a table with one partition per row.
Partition Chip View—Shows a floorplan view of the XLR cells and any assigned partitions.
Partition Interface Assignments—Allows you to place Interface cells in specific XLR locations manually within an export partition.
Partitions streamline and accelerate the development process by utilizing modular design and design reuse. Use the Efinity Partition Planner to support design reuse through partitioning in Titanium and Topaz family FPGAs.
To learn more about the Efinity Partition Planner, see the Efinity Software User Guide. Additionally, the Efinity Partitioning and Preservation Flows Tutorial outlines the processes of placing partitions and using mixed-preservation and team-based designs.