Partner

UNO Laboratories, Ltd. provides Single-Stage RISC-V core (Trinita®) based on its patent. Trinita® connects the instruction memory (RAM) directly to the decoder and processes one instruction cycle in one stage (one clock), eliminating the need for branch prediction functions. With no pipeline-like processing waste or hazards, Trinita® delivers real-time performance and high power efficiency. It is ideal for IoT sensor nodes, surveillance systems, and edge computing such as AI and image processing. | Free trial of Trinita® for Sapphire SoC available on GitHub: https://github.com/unolabo/ | Replacing the VexRiscv core in Sapphire SoC with Trinita® doubles power efficiency: - For T8/T20/Ti60 (Implementable in other Efinix® FPGAs) - With encryption and 1 hour usage limit