Resource Utilization and Performance
Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
| FPGA | FSM Count | Clock | Logic Elements (Logic, Adders, Flipflops, etc.) | Memory Block | Multiplier Block | Efinity® Version1 |
|---|---|---|---|---|---|---|
| T20 F256 C4 | 1 | 1/16 (6.3%) | 106/19,728 (0.5%) | 0/204 (0%) | 0/36 (0%) | 2024.1 |
| 8 | 1/16 (6.3%) | 710/19,728 (3.6%) | 0/204 (0%) | 0/36 (0%) |
1 Using Verilog HDL.