Functional Description
The Trion PLL Auto-Reset core applies to user-instantiated PLLs. The core
uses the PLL's reset (RSTN) and locked (LOCKED)
signals. From the core’s perspective, the LOCKED pin is an input
from PLL after the core's reset signal goes high. If the LOCKED pin
remains low after exceeding tLOCK duration, the core outputs an
active-low pulse signal to the PLL's RSTN pin to reset the PLL.
There are 2 methods to implement the monitoring function, which includes a finite
state machine (FSM).
- Instantiate one FSM for each PLL.
- Allow several PLLs to share the same FSM to reduce resource utilization. Sharing an FSM can increase the time it takes for the PLL to lock because each PLL operates independently, which may cause some PLLs to lose lock after the other PLLs are locked.
