Introduction

The Trion PLL Auto-Reset core improves the PLL functionality by efficiently resetting the PLLs. Trion FPGAs have phase-locked loops (PLLs) situated at the corners of the FPGA, which are used to generate clock signals for your design. You can use PLLs to compensate for clock skew or delay through external or internal feedback, thus meeting the timing requirements for advanced applications.

Use the IP Manager to select IP, customize it, and generate files. The Trion PLL Auto-Reset core has an interactive wizard to help you set parameters. The wizard also has options to create a testbench and/or example design targeting an Efinix® development board.