Memory Coherency

The High-Performance Sapphire RV32 SoC implements memory coherency using a DMA channel, also known as an AXI slave channel, through a write buffer unit. The write buffer unit resides in the AXI interconnect, which connects the routes between the CPU and DMA to external memory. The write buffer unit has snooper logic that monitors data traffic and invalidates the part when one master overwrites the data previously written by another master. This ensures that all masters, both CPU and DMA, consistently operate on the same data. However, the write buffer unit can be disabled in the Interface Designer. There is no data coherence if you disable the write buffer unit.