Revision History
| Date | Version | Description |
|---|---|---|
| May 2026 | 3.2 | Changed document title from Sapphire High-Performance RISC-V SoC Data
Sheet to High-Performance Sapphire RV32 SoC Data Sheet. Changed content
Sapphire high-performance RISC-V SoC to High-Performance Sapphire RV32
SoC. (DOC-2929) Added Cache Policy and Memory Coherency topic.
(DOC-2772) |
| January 2026 | 3.1 | Updated FPGA Support for Titanium (Ti85 and Ti165) and Topaz devices. (DOC-2875) |
| November 2025 | 3.0 | Change AXI master/slave interface 0/1. (DOC-2683) In Watchdog
Timer Interface, Added Disable Register: 0x0000_0008. Updated
Heatbeat Register: 0x0000_0000 and Enable Register:
0x0000_0004. |
| December 2024 | 2.0 | Updated Performance Benchmark. (DOC-2098) Added Watchdog Timer
Register Map. Removed vector mode from both Machine
Trap-Vector Base-Address Register (mtvec): 0x305 and Supervisor
Trap-Vector Base Address Register (stvec): 0x305. |
| January 2024 | 1.0 | Initial release. |