Cache Policy

The High-Performance Sapphire RV32 SoC implements a write-through cache policy to ensure that every store operation updates both the L1 cache and the next level of memory simultaneously, thereby maintaining full consistency between the cache and the main memory. When a write hits in the cache, the data is written to the cache line and immediately propagated to external memory through the system bus, eliminating the need for 'dirty' bits or deferred write-back mechanisms. In the case of a cache miss, the design commonly follows a write-no-allocate policy, where the write is sent directly to memory without allocating a new cache line, thereby avoiding unnecessary cache pollution for data that may not be reused.