Sapphire SoC DS Sapphire SoC UG Sapphire HP SoC DS Sapphire HP SoC UG RISC-V Embedded IDE UG Board Support Package
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watchdog.h
Go to the documentation of this file.
1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6#ifndef WATCHDOG_H
7#define WATCHDOG_H
8
16
17#include "type.h"
18#include "soc.h"
19#include "riscv.h"
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
44
45/* ========================================================================== */
46/* SUB-GROUP : Data Types */
47/* ========================================================================== */
54
60 typedef enum {
61 WDG_TIMER_CLEAR = 0xAD68E70D,
62 WDG_TIMER_UNLOCK = 0x3C21B925,
63 WDG_TIMER_LOCK = 0x3C21B924
65
67 // End of WDG_ENUM group
69
70/* ========================================================================== */
71/* SUB-GROUP : DATA STRUCTS */
72/* ========================================================================== */
123
156 // End of WDG_Types group
158
159
160/* ========================================================================== */
161/* SUB-GROUP: FUNCTIONS */
162/* ========================================================================== */
163
181
209 void watchdog_enable(watchdog_instance_t *inst, u32 mask);
216 void watchdog_disable(watchdog_instance_t *inst, u32 mask);
218
237
261 void watchdog_setCounterLimit(watchdog_instance_t *inst, u32 counterId, u32 value);
263 // End of WDG_Funcs group
265
266
267
268#ifdef __cplusplus
269}
270#endif // End of MAIN WDG Group
272
273#endif // WATCHDOG_H
watchdog_heartbeat_t
Value for the timer to generate a detection pulse.
Definition watchdog.h:60
@ WDG_TIMER_LOCK
Lock WDG Timer.
Definition watchdog.h:63
@ WDG_TIMER_UNLOCK
Unlock WDG Timer.
Definition watchdog.h:62
@ WDG_TIMER_CLEAR
Reset WDG Timer.
Definition watchdog.h:61
void watchdog_enable(watchdog_instance_t *inst, u32 mask)
Enable Watchdog Counters.
Definition watchdog.c:64
void watchdog_clear(watchdog_instance_t *inst)
Send Clear Heartbeat to Watchdog.
Definition watchdog.c:47
void watchdog_applyConfig(watchdog_instance_t *inst)
Apply the software configuration to the hardware.
Definition watchdog.c:81
void watchdog_lock(watchdog_instance_t *inst)
Send Lock Heartbeat to Watchdog.
Definition watchdog.c:53
void watchdog_unlock(watchdog_instance_t *inst)
Send Unlock Heartbeat to Watchdog.
Definition watchdog.c:58
u32 watchdog_getCounterValue(watchdog_instance_t *inst, u32 counterId)
Get current Counter Value.
Definition watchdog.c:22
void watchdog_setCounterLimit(watchdog_instance_t *inst, u32 counterId, u32 value)
Set Watchdog Counter Limit.
Definition watchdog.c:34
u32 watchdog_getEnable(watchdog_instance_t *inst)
Get Watchdog Enable Register.
Definition watchdog.c:75
void watchdog_disable(watchdog_instance_t *inst, u32 mask)
Disable Watchdog Counters.
Definition watchdog.c:69
void watchdog_setPrescaler(watchdog_instance_t *inst, u32 value)
Set Watchdog Prescaler Value.
Definition watchdog.c:28
void watchdog_setHeartBeat(watchdog_instance_t *inst, watchdog_heartbeat_t value)
Set Watchdog Heartbeat Action.
Definition watchdog.c:42
RISC-V related functions and definitions.
Watchdog hardware register map.
Definition watchdog.h:109
u32 WDG_COUNTER_VALUE_1
Address Offset: 0xC4 - Counter 1 Value Register.
Definition watchdog.h:120
u32 WDG_ENABLE
Address Offset: 0x04 - Enable Register.
Definition watchdog.h:111
u32 WDG_COUNTER_LIMIT_1
Address Offset: 0x84 - Counter 1 Limit Register.
Definition watchdog.h:117
u32 WDG_COUNTER_LIMIT_0
Address Offset: 0x80 - Counter 0 Limit Register.
Definition watchdog.h:116
u32 WDG_HEARTBEAT
Address Offset: 0x00 - Heartbeat Register.
Definition watchdog.h:110
u32 reserved2[(0x00C0 - 0x88)/4U]
Reserved Space (0x88 to 0xBF).
Definition watchdog.h:118
u32 WDG_DISABLE
Address Offset: 0x08 - Disable Register.
Definition watchdog.h:112
u32 reserved0[(0x0040 - 0xC)/4U]
Reserved Space (0x0C to 0x3F).
Definition watchdog.h:113
u32 WDG_PRESCALER
Address Offset: 0x40 - Prescaler Register.
Definition watchdog.h:114
u32 reserved1[(0x0080 - 0x44)/4U]
Reserved Space (0x44 to 0x7F).
Definition watchdog.h:115
u32 WDG_COUNTER_VALUE_0
Address Offset: 0xC0 - Counter 0 Value Register.
Definition watchdog.h:119
Watchdog instance. Holds the software registers and hardware pointer.
Definition watchdog.h:133
u32 prescaler
Prescaler value.
Definition watchdog.h:144
watchdog_hwreg_t * hwreg
Definition watchdog.h:134
uint32_t u32
Definition type.h:22