Sapphire SoC DS Sapphire SoC UG Sapphire HP SoC DS Sapphire HP SoC UG RISC-V Embedded IDE UG Board Support Package
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watchdog.c
Go to the documentation of this file.
1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
15#include "watchdog/watchdog.h"
16
17
18/*----------------------------------------------------------------------------*/
19/* Function implementations */
20/*----------------------------------------------------------------------------*/
21
23{
24 volatile u32 *p = (volatile u32 *)(uintptr_t)&inst->hwreg->WDG_COUNTER_VALUE_0;
25 return p[counterId];
26}
27
29{
30 inst->hwreg->WDG_PRESCALER = value;
31}
32
33
35{
36 if (counterId >1) return;
37 volatile u32 *p = (volatile u32 *)(uintptr_t)&inst->hwreg->WDG_COUNTER_LIMIT_0;
38 p[counterId] = value;
39}
40
41
46
51
52
57
62
63
65{
66 inst->hwreg->WDG_ENABLE |= mask;
67}
68
70{
71 inst->hwreg->WDG_DISABLE &= ~mask;
72}
73
74
79
80
82{
86
87 // Safety Check for HeartBeat Config
88 if ((inst->heartbeat == WDG_TIMER_CLEAR) ||
89 (inst->heartbeat == WDG_TIMER_UNLOCK) ||
90 (inst->heartbeat == WDG_TIMER_LOCK))
91 {
93 }
94
95 // Counter 0 Handling
96 if (inst->enable[0]) {
97 watchdog_enable(inst, 0x1); // Enable Bit 0
98 } else {
99 watchdog_disable(inst, 0x1); // Disable Bit 0 (Must pass 1, not 0!)
100 }
101
102 // Counter 1 Handling
103 if (inst->enable[1]) {
104 watchdog_enable(inst, 0x2); // Enable Bit 1 (1 << 1)
105 } else {
106 watchdog_disable(inst, 0x2); // Disable Bit 1
107 }
108}
109
watchdog_heartbeat_t
Value for the timer to generate a detection pulse.
Definition watchdog.h:60
@ WDG_TIMER_LOCK
Lock WDG Timer.
Definition watchdog.h:63
@ WDG_TIMER_UNLOCK
Unlock WDG Timer.
Definition watchdog.h:62
@ WDG_TIMER_CLEAR
Reset WDG Timer.
Definition watchdog.h:61
void watchdog_enable(watchdog_instance_t *inst, u32 mask)
Enable Watchdog Counters.
Definition watchdog.c:64
void watchdog_clear(watchdog_instance_t *inst)
Send Clear Heartbeat to Watchdog.
Definition watchdog.c:47
void watchdog_applyConfig(watchdog_instance_t *inst)
Apply the software configuration to the hardware.
Definition watchdog.c:81
void watchdog_lock(watchdog_instance_t *inst)
Send Lock Heartbeat to Watchdog.
Definition watchdog.c:53
void watchdog_unlock(watchdog_instance_t *inst)
Send Unlock Heartbeat to Watchdog.
Definition watchdog.c:58
u32 watchdog_getCounterValue(watchdog_instance_t *inst, u32 counterId)
Get current Counter Value.
Definition watchdog.c:22
void watchdog_setCounterLimit(watchdog_instance_t *inst, u32 counterId, u32 value)
Set Watchdog Counter Limit.
Definition watchdog.c:34
u32 watchdog_getEnable(watchdog_instance_t *inst)
Get Watchdog Enable Register.
Definition watchdog.c:75
void watchdog_disable(watchdog_instance_t *inst, u32 mask)
Disable Watchdog Counters.
Definition watchdog.c:69
void watchdog_setPrescaler(watchdog_instance_t *inst, u32 value)
Set Watchdog Prescaler Value.
Definition watchdog.c:28
void watchdog_setHeartBeat(watchdog_instance_t *inst, watchdog_heartbeat_t value)
Set Watchdog Heartbeat Action.
Definition watchdog.c:42
u32 WDG_ENABLE
Address Offset: 0x04 - Enable Register.
Definition watchdog.h:111
u32 WDG_COUNTER_LIMIT_0
Address Offset: 0x80 - Counter 0 Limit Register.
Definition watchdog.h:116
u32 WDG_HEARTBEAT
Address Offset: 0x00 - Heartbeat Register.
Definition watchdog.h:110
u32 WDG_DISABLE
Address Offset: 0x08 - Disable Register.
Definition watchdog.h:112
u32 WDG_PRESCALER
Address Offset: 0x40 - Prescaler Register.
Definition watchdog.h:114
u32 WDG_COUNTER_VALUE_0
Address Offset: 0xC0 - Counter 0 Value Register.
Definition watchdog.h:119
Watchdog instance. Holds the software registers and hardware pointer.
Definition watchdog.h:133
u32 prescaler
Prescaler value.
Definition watchdog.h:144
watchdog_hwreg_t * hwreg
Definition watchdog.h:134
uint32_t u32
Definition type.h:22
Watchdog driver API definitions.