#include <watchdog.h>

Data Fields
u32	WDG_HEARTBEAT
	Address Offset: 0x00 - Heartbeat Register.
u32	WDG_ENABLE
	Address Offset: 0x04 - Enable Register.
u32	WDG_DISABLE
	Address Offset: 0x08 - Disable Register.
u32	reserved0 [(0x0040 - 0xC)/4U]
	Reserved Space (0x0C to 0x3F).
u32	WDG_PRESCALER
	Address Offset: 0x40 - Prescaler Register.
u32	reserved1 [(0x0080 - 0x44)/4U]
	Reserved Space (0x44 to 0x7F).
u32	WDG_COUNTER_LIMIT_0
	Address Offset: 0x80 - Counter 0 Limit Register.
u32	WDG_COUNTER_LIMIT_1
	Address Offset: 0x84 - Counter 1 Limit Register.
u32	reserved2 [(0x00C0 - 0x88)/4U]
	Reserved Space (0x88 to 0xBF).
u32	WDG_COUNTER_VALUE_0
	Address Offset: 0xC0 - Counter 0 Value Register.
u32	WDG_COUNTER_VALUE_1
	Address Offset: 0xC4 - Counter 1 Value Register.

Detailed Description

Watchdog hardware register map.

Note: This is the main structure that maps directly onto the Watchdog peripheral memory-mapped register layout.

Definition at line 108 of file watchdog.h.

Field Documentation

◆ reserved0

u32 watchdog_hwreg_t::reserved0[(0x0040 - 0xC)/4U]

Reserved Space (0x0C to 0x3F).

Definition at line 113 of file watchdog.h.

◆ reserved1

u32 watchdog_hwreg_t::reserved1[(0x0080 - 0x44)/4U]

Reserved Space (0x44 to 0x7F).

Definition at line 115 of file watchdog.h.

◆ reserved2

u32 watchdog_hwreg_t::reserved2[(0x00C0 - 0x88)/4U]

Reserved Space (0x88 to 0xBF).

Definition at line 118 of file watchdog.h.

◆ WDG_COUNTER_LIMIT_0

u32 watchdog_hwreg_t::WDG_COUNTER_LIMIT_0

Address Offset: 0x80 - Counter 0 Limit Register.

Definition at line 116 of file watchdog.h.

◆ WDG_COUNTER_LIMIT_1

u32 watchdog_hwreg_t::WDG_COUNTER_LIMIT_1

Address Offset: 0x84 - Counter 1 Limit Register.

Definition at line 117 of file watchdog.h.

◆ WDG_COUNTER_VALUE_0

u32 watchdog_hwreg_t::WDG_COUNTER_VALUE_0

Address Offset: 0xC0 - Counter 0 Value Register.

Definition at line 119 of file watchdog.h.

◆ WDG_COUNTER_VALUE_1

u32 watchdog_hwreg_t::WDG_COUNTER_VALUE_1

Address Offset: 0xC4 - Counter 1 Value Register.

Definition at line 120 of file watchdog.h.

◆ WDG_DISABLE

u32 watchdog_hwreg_t::WDG_DISABLE

Address Offset: 0x08 - Disable Register.

Definition at line 112 of file watchdog.h.

◆ WDG_ENABLE

u32 watchdog_hwreg_t::WDG_ENABLE

Address Offset: 0x04 - Enable Register.

Definition at line 111 of file watchdog.h.

◆ WDG_HEARTBEAT

u32 watchdog_hwreg_t::WDG_HEARTBEAT

Address Offset: 0x00 - Heartbeat Register.

Definition at line 110 of file watchdog.h.

◆ WDG_PRESCALER

u32 watchdog_hwreg_t::WDG_PRESCALER

Address Offset: 0x40 - Prescaler Register.

Definition at line 114 of file watchdog.h.

The documentation for this struct was generated from the following file:

C:/Users/JasonLau/Downloads/workspace_local/GitLab/efx_IP/efx_soc_rv64/embedded_sw/software/standalone/driver/watchdog/watchdog.h

Data Fields