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RISC-V Core Driver
System Core

Overview

RISC-V specific driver.

This module provides functions to configure and control RISC-V specific registers and interrupt behavior.

Usage & Initialization.

This is an example show how to configure RISC-V specific registers and interrupt behavior.

In reality, user are encouraged to use irq_enable, irq_setTrapVector, and irq_setType APIs to configure the interrupt behavior.

#include "riscv.h"
void isrInit(){
csr_set(mie, MIE_MTIE); // Enable Machine Timer Interrupt
csr_set(mstatus, MSTATUS_MIE); // Enable Global Interrupts
csr_write(mtvec, trap_entry); // Set the trap vector to the address of trap_entry
}
trap_entry
void trap_entry(void)
The Main Trap Entry Point (Naked).
Definition mtrap.c:129
MIE_MTIE
#define MIE_MTIE
Machine Timer Interrupt Enable (Bit 7).
Definition riscv.h:132
csr_set
#define csr_set(csr, val)
This function is used to set a CSR to a specified value.
Definition riscv.h:278
csr_write
#define csr_write(csr, val)
This function is used to write a value to a CSR.
Definition riscv.h:249
riscv.h
RISC-V related functions and definitions.
See also
irq.c for more details on irq_enable, irq_setTrapVector, and irq_setType APIs.

Topics

 API Functions
 Function definitions for RISCV driver.
 Register Definitions
 Register bitmasks and offsets.