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riscv.h
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1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6#ifndef RISC_V_H_
7#define RISC_V_H_
8
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
30
31/* ========================================================================== */
32/* SUB-GROUP : REGISTER DEFINITIONS */
33/* ========================================================================== */
34
44 #define CAUSE_SUPERVISOR_SOFTWARE 1
45 #define CAUSE_MACHINE_SOFTWARE 3
46 #define CAUSE_USER_TIME 4
47 #define CAUSE_SUPERVISOR_TIMER 5
48 #define CAUSE_MACHINE_TIMER 7
49 #define CAUSE_USER_EXTERNAL 8
50 #define CAUSE_SCALL 9
51 #define CAUSE_MACHINE_EXTERNAL 11
53
57 #define CAUSE_INSTRUCTION_ADDR_MISALIGNED 0
58 #define CAUSE_ACCESS_FAULT 1
59 #define CAUSE_ILLEGAL_INSTRUCTION 2
60 #define CAUSE_BREAKPOINT 3
61 #define CAUSE_LOAD_ADDR_MISALIGNED 4
62 #define CAUSE_LOAD_ACCESS_FAULT 5
63 #define CAUSE_STORE_AMO_ADDR_MISALIGNED 6
64 #define CAUSE_STORE_AMO_ACCESS_FAULT 7
65 #define CAUSE_ENV_CALL_U_MODE 8
66 #define CAUSE_ENV_CALL_S_MODE 9
67 #define CAUSE_ENV_CALL_M_MODE 11
68 #define CAUSE_INSTRUCTION_PAGE_FAULT 12
69 #define CAUSE_LOAD_PAGE_FAULT 13
70 #define CAUSE_STORE_AMO_PAGE_FAULT 15
72
76 #define MEDELEG_INSTRUCTION_PAGE_FAULT (1 << 12)
77 #define MEDELEG_LOAD_PAGE_FAULT (1 << 13)
78 #define MEDELEG_STORE_PAGE_FAULT (1 << 15)
79 #define MEDELEG_USER_ENVIRONNEMENT_CALL (1 << 8)
80 #define MIDELEG_SUPERVISOR_SOFTWARE (1 << 1)
81 #define MIDELEG_SUPERVISOR_TIMER (1 << 5)
82 #define MIDELEG_SUPERVISOR_EXTERNAL (1 << 9)
87 #define MIE_MSIE (1 << CAUSE_MACHINE_SOFTWARE)
88 #define MIE_MTIE (1 << CAUSE_MACHINE_TIMER)
89 #define MIE_MEIE (1 << CAUSE_MACHINE_EXTERNAL)
94 #define RDCYCLE 0xC00
95 #define RDTIME 0xC01
96 #define RDINSTRET 0xC02
97 #define RDCYCLEH 0xC80
98 #define RDTIMEH 0xC81
99 #define RDINSTRETH 0xC82
102 #define MIP_STIP (1 << 5)
103 #define MSTATUS_UIE 0x00000001
104 #define MSTATUS_SIE 0x00000002
105 #define MSTATUS_HIE 0x00000004
106 #define MSTATUS_MIE 0x00000008
107 #define MSTATUS_UPIE 0x00000010
108 #define MSTATUS_SPIE 0x00000020
109 #define MSTATUS_HPIE 0x00000040
110 #define MSTATUS_MPIE 0x00000080
111 #define MSTATUS_SPP 0x00000100
112 #define MSTATUS_HPP 0x00000600
113 #define MSTATUS_MPP 0x00001800
114 #define MSTATUS_FS 0x00006000
115 #define MSTATUS_XS 0x00018000
116 #define MSTATUS_MPRV 0x00020000
117 #define MSTATUS_SUM 0x00040000
118 #define MSTATUS_MXR 0x00080000
119 #define MSTATUS_TVM 0x00100000
120 #define MSTATUS_TW 0x00200000
121 #define MSTATUS_TSR 0x00400000
122 #define MSTATUS32_SD 0x80000000
123 #define MSTATUS_UXL 0x0000000300000000
124 #define MSTATUS_SXL 0x0000000C00000000
125 #define MSTATUS64_SD 0x8000000000000000
126 #define SSTATUS_UIE 0x00000001
127 #define SSTATUS_SIE 0x00000002
128 #define SSTATUS_UPIE 0x00000010
129 #define SSTATUS_SPIE 0x00000020
130 #define SSTATUS_SPP 0x00000100
131 #define SSTATUS_FS 0x00006000
132 #define SSTATUS_XS 0x00018000
133 #define SSTATUS_SUM 0x00040000
134 #define SSTATUS_MXR 0x00080000
135 #define SSTATUS32_SD 0x80000000
136 #define SSTATUS_UXL 0x0000000300000000
137 #define SSTATUS64_SD 0x8000000000000000
138 #define PMP_R 0x01
139 #define PMP_W 0x02
140 #define PMP_X 0x04
141 #define PMP_A 0x18
142 #define PMP_L 0x80
143 #define PMP_SHIFT 2
144 #define PMP_TOR 0x08
145 #define PMP_NA4 0x10
146 #define PMP_NAPOT 0x18
148
150
151/* ========================================================================== */
152/* FUNCTION PROTOTYPES */
153/* ========================================================================== */
154
161
172 #define csr_swap(csr, val) \
173 ({ \
174 unsigned long __v = (unsigned long)(val); \
175 __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \
176 : "=r" (__v) : "rK" (__v)); \
177 __v; \
178 })
179
188 #define csr_read(csr) \
189 ({ \
190 register unsigned long __v; \
191 __asm__ __volatile__ ("csrr %0, " #csr \
192 : "=r" (__v)); \
193 __v; \
194 })
195
196
205 #define csr_write(csr, val) \
206 ({ \
207 unsigned long __v = (unsigned long)(val); \
208 __asm__ __volatile__ ("csrw " #csr ", %0" \
209 : : "rK" (__v)); \
210 })
211
221 #define csr_read_set(csr, val) \
222 ({ \
223 unsigned long __v = (unsigned long)(val); \
224 __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \
225 : "=r" (__v) : "rK" (__v)); \
226 __v; \
227 })
228
234 #define csr_set(csr, val) \
235 ({ \
236 unsigned long __v = (unsigned long)(val); \
237 __asm__ __volatile__ ("csrs " #csr ", %0" \
238 : : "rK" (__v)); \
239 })
240
247 #define csr_read_clear(csr, val) \
248 ({ \
249 unsigned long __v = (unsigned long)(val); \
250 __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \
251 : "=r" (__v) : "rK" (__v)); \
252 __v; \
253 })
254
263 #define csr_clear(csr, val) \
264 ({ \
265 unsigned long __v = (unsigned long)(val); \
266 __asm__ __volatile__ ("csrc " #csr ", %0" \
267 : : "rK" (__v)); \
268 })
269
271 /*******************************************************************************
272 * @brief Definition of symbolic constants for RISC-V registers.
273 * @note
274 * General-purpose registers (x0-x31):
275 * Lines 1-32 define constants regnum_x0 through regnum_x31 for the 32 general-
276 * purpose registers.
277 *
278 * Special-purpose registers:
279 * Lines 34-63 define constants for special-purpose registers such as zero, ra,
280 * sp, gp, tp, and the temporary registers t0-t6.
281 *
282 * Custom register:
283 * Line 65 defines a symbolic constant CUSTOM0 for a custom register, which
284 * could be used for a specific purpose defined by the programmer.
285 *
286 ******************************************************************************/
287 asm(".set regnum_x0 , 0");
288 asm(".set regnum_x1 , 1");
289 asm(".set regnum_x2 , 2");
290 asm(".set regnum_x3 , 3");
291 asm(".set regnum_x4 , 4");
292 asm(".set regnum_x5 , 5");
293 asm(".set regnum_x6 , 6");
294 asm(".set regnum_x7 , 7");
295 asm(".set regnum_x8 , 8");
296 asm(".set regnum_x9 , 9");
297 asm(".set regnum_x10 , 10");
298 asm(".set regnum_x11 , 11");
299 asm(".set regnum_x12 , 12");
300 asm(".set regnum_x13 , 13");
301 asm(".set regnum_x14 , 14");
302 asm(".set regnum_x15 , 15");
303 asm(".set regnum_x16 , 16");
304 asm(".set regnum_x17 , 17");
305 asm(".set regnum_x18 , 18");
306 asm(".set regnum_x19 , 19");
307 asm(".set regnum_x20 , 20");
308 asm(".set regnum_x21 , 21");
309 asm(".set regnum_x22 , 22");
310 asm(".set regnum_x23 , 23");
311 asm(".set regnum_x24 , 24");
312 asm(".set regnum_x25 , 25");
313 asm(".set regnum_x26 , 26");
314 asm(".set regnum_x27 , 27");
315 asm(".set regnum_x28 , 28");
316 asm(".set regnum_x29 , 29");
317 asm(".set regnum_x30 , 30");
318 asm(".set regnum_x31 , 31");
319 asm(".set regnum_zero, 0");
320 asm(".set regnum_ra , 1");
321 asm(".set regnum_sp , 2");
322 asm(".set regnum_gp , 3");
323 asm(".set regnum_tp , 4");
324 asm(".set regnum_t0 , 5");
325 asm(".set regnum_t1 , 6");
326 asm(".set regnum_t2 , 7");
327 asm(".set regnum_s0 , 8");
328 asm(".set regnum_s1 , 9");
329 asm(".set regnum_a0 , 10");
330 asm(".set regnum_a1 , 11");
331 asm(".set regnum_a2 , 12");
332 asm(".set regnum_a3 , 13");
333 asm(".set regnum_a4 , 14");
334 asm(".set regnum_a5 , 15");
335 asm(".set regnum_a6 , 16");
336 asm(".set regnum_a7 , 17");
337 asm(".set regnum_s2 , 18");
338 asm(".set regnum_s3 , 19");
339 asm(".set regnum_s4 , 20");
340 asm(".set regnum_s5 , 21");
341 asm(".set regnum_s6 , 22");
342 asm(".set regnum_s7 , 23");
343 asm(".set regnum_s8 , 24");
344 asm(".set regnum_s9 , 25");
345 asm(".set regnum_s10 , 26");
346 asm(".set regnum_s11 , 27");
347 asm(".set regnum_t3 , 28");
348 asm(".set regnum_t4 , 29");
349 asm(".set regnum_t5 , 30");
350 asm(".set regnum_t6 , 31");
351 asm(".set CUSTOM0 , 0x0B");
352 asm(".set CUSTOM1 , 0x2B");
353 asm(".set CUSTOM2 , 0x5B");
355
370 #define opcode_R(opcode, func3, func7, rs1, rs2) \
371 ({ \
372 register unsigned long __v; \
373 asm volatile( \
374 ".word ((" #opcode ") | (regnum_%0 << 7) | (regnum_%1 << 15) | (regnum_%2 << 20) | ((" #func3 ") << 12) | ((" #func7 ") << 25));" \
375 : [rd] "=r" (__v) \
376 : "r" (rs1), "r" (rs2) \
377 ); \
378 __v; \
379 })
380
388 #define cfu_type_R(func3, func7, rs1, rs2) opcode_R(CUSTOM0, func3, func7, rs1, rs2)
389
398 #define cfu_push(func3, func7, rs1, rs2) opcode_R(CUSTOM1, func3, func7, rs1, rs2)
399 #define cfu_pop2() ({ register unsigned long __v; asm volatile( ".word ((0x5B) | (regnum_%0 << 7));" : [rd] "=r" (__v) : ); __v; })
400 #define cfu_pop() \
401 ({ \
402 register unsigned long __v; \
403 asm volatile( \
404 ".word ((0x5B) | (regnum_%0 << 7));" \
405 : [rd] "=r" (__v) \
406 : \
407 ); \
408 __v; \
409 })
410 // End of RISCV_Funcs group
412
413#ifdef __cplusplus
414}
415#endif // C_plusplus
416 // End of RISCV Group
418#endif //RISC_V_H_