Placement
- Place the DRAM device as near as possible to the Titanium™ FPGA.
- Rotate the IC orientation to have direct routing especially for high-speed traces.
- Avoid routing high-speed differential traces under power connectors, power delivery inductors, other interface connectors, crystal, oscillators, clock synthesizers, magnetic devices, or integrated circuits that use or duplicate clocks.
- Keep large spacing (>100 mils) between high-speed traces, vias, and pads of
high-noise power nets.Note: High-noise power nets include nets like the switching node (phase node) of a voltage regulator module (VRM), 12 V power net, and high current transient power net.
Note: Refer to Titanium™ Interactive
Hardware Design Checklist and Guidelines in Efinix® Support Center for further details.
| PCB Layer | 4 Layers | 8 Layers | 8 Layers | 12 Layers |
|---|---|---|---|---|
| L1 | DM/DQ/DQS/CA | CA | NA | CA |
| L2 | Power/GND | GND | GND | GND |
| L3 | Power/GND | DM/DQ/DQS | DM/DQ/DQS | DM/DQ/DQS |
| L4 | DM/DQ/DQS/CA | Power/GND | Power/GND | GND |
| L5 | - | Power/GND | Power/GND | Power |
| L6 | - | DM/DQ/DQS | DM/DQ/DQS | Power |
| L7 | - | GND | GND | GND |
| L8 | - | NA | CA | DM/DQ/DQS |
| L9 | - | - | - | GND |
| L10 | - | - | - | DM/DQ/DQS |
| L11 | - | - | - | GND |
| L12 | - | - | - | NA |