Clock Signals

The DDR DRAM interface requires different master DDR_CK and DDR_CK_N clock inputs. All address and control signals are sampled on the rising edge of DDR_CK.

Ensure that the DRAM has a clean differential clock input.
Balance the output data so that each data word has the same valid time as all of the signals.
Match the DDR_CK trace length to the DDR_CK_N trace length by referring to Table 1. It is applicable for multiple clock pairs that are transmitted from the controller to components.
Route all the CK, A, CKE, and CS in the same PCB layer.

Important: If you use the write leveling feature, the CK_(n-1) trace length must be longer than the DQS_(n-1) trace length. n is the number of DDR device used. Refer to Table 1 for more skew control recommendations.