Length Matching

Efinix® recommends that you comply to the length matching tolerance in Table 1. The length matching recommendation is derived from the total signal length. The following figure illustrates the total signal length.

Figure 1. Total Signal Length

The total signal length is (FPGA package net length + total PCB trace length). You can obtain the FPGA package net length file from Board Design page of the Support Center.

The distance requirement of the PCB trace length involving the Blind vias is as follows:
  • Maximum distance between FPGA ball and Blind via – 70 mils.
  • Maximum distance between DRAM ball and Blind via – 200 mils.

For example, if the package delays for the three pins reported in the FPGA package net length file are:

  • Pin A1—110 ps
  • Pin A2—70 ps
  • Pin A3—150 ps

To match the total signal length of 3 pins, you would need to have a PCB trace for Pin A1 that is 40 ps longer than Pin A3 and a PCB trace for Pin A2 that is 80 ps longer than Pin A3.