Introduction

This user guide explains the recommended printed circuit board (PCB) layout design for the Titanium™ DDR DRAM interface signals. You must have basic knowledge of high-speed PCB layout design. You should implement these best practices as well as understand your PCB layout options when designing applications that incorporate DDR DRAM. Good signal integrity (SI) is important because poorly transmitted signals can significantly lower the data valid margin at the receiver.

Table 1. Titanium™ FPGA Pin Symbol and Description
Symbol Titanium™ FPGA Pin Name Description
x16 x32
DDR LPDDR4 and LPDDR4x external memory interface
DRAM External memory
VDD VDD_PHY LPDDR4 and LPDDR4x digital power supply
VDDQ VDDQ_PHY LPDDR4 and LPDDR4x I/O power supply
CA Clock/control/command/address signals
SNR Signal-to-noise ratio
Clock Signals
CK DDR_CK, DDR_CK_N Differential clock
Command /Address Signals
A DDR_A[5:0] Command/address bus
Control Signals
CKE DDR_CKE[1:0] Clock enable
CS DDR_CS_N[3:0] Chip select
Data Signals
DM DDR_DM[1:0] DDR_DM[3:0] Data-mask signal enable
DQ DDR_DQ[15:0] DDR_DQ[31:0] Data bus
DQS DDR_DQS[1:0], DDR_DQS_N[1:0] DDR_DQS[3:0], DDR_DQS_N[3:0] Differential data strobe

In the document, the recommendation is based on FR4 material with a dielectric constant (Dk) value of 3.7 to 3.9 and a disspation factor (Df) value of 0.012 to 0.02:
  • Performance can vary depending on FR4 material, PCB stackup, trace impedance (Zo), and layout implementation.
  • The layout design must include the package net length for length matching.

Efinix® recommends that you perform SI analysis after completing the layout design.