Revision History

Table 1. Revision History
Date Document Version IP Version Description
June 2025 1.9 Unidirectional – 5.7
Bidirectional – 5.9
Update missing port, TxTriggerEsc[3:0]
Added TxTriggerEsc [3:0] in PHY-Protocol Interface table.
May 2025 1.8 Unidirectional – 5.7
Bidirectional – 5.9
Update default paramater value. (SIP-910)
Example design I/O bank update (HVIO 3.3 V). (SIP-907)
Updated Customizing the MIPI D-PHY TX Controller.
November 2024 1.7 5.8 Added Topaz in Features and Device Support. (DOC-2102)
Added IP Version in Revision History. (DOC-2185)
September 2024 1.6 Added 8 lanes support in Features and Table 1. (SIP-677)
Updated tCLK_PRE and tCLK_POST in Table 1. (DOC-2078)
June 2024 1.5 Revised supported lane number. Removed 8 lane in Features and table MIPI D-PHY TX Controller Core Parameter. (SIP-578)
Added important note in Example Design and Testbench regarding using default parameters options only. (DOC-1781)
June 2023 1.4
Added Device Support and release notes sections. (DOC-1234)
Updated supported data rate. (DOC-1217)
Updated HS BYTECLK and CLOCK_FREQ_MHZ parameter.
Editorial changes.
February 2023 1.3 Added note about the resource and performance values in the resource and utilization table are for guidance only.
January 2022 1.2 Updated resource utilization table. (DOC-700)
October 2021 1.1 Added note to state that the fMAX in Resource Utilization and Performance, and Example Design Implementation tables were based on default parameter settings.
Updated design example target board to production Titanium Ti60 F225 Development Board and updated Resource Utilization and Performance, and Example Design Implementation tables. (DOC-553)
June 2021 1.0 Initial release.