Ports
| Port | Direction | Description |
|---|---|---|
| clk | Input | IP core clock consumed by controller logics. 100 MHz. |
| reset_n | Input | IP core reset signal. |
| clk_byte_HS | Input | MIPI TX parallel clock. This is a HS mode transmission clock. |
| reset_byte_HS_n | Input | MIPI TX parallel clock reset signal. |
| Port | Direction | Description |
|---|---|---|
| Tx_LP_CLK_N | Output | LP mode TX clock single-ended N signal. |
| Tx_LP_CLK_P | Output | LP mode TX clock single-ended P signal. |
| Tx_LP_CLK_N_OE | Output | Output enable for LP mode TX clock single-ended N signal. |
| Tx_LP_CLK_P_OE | Output | Output enable for LP mode TX clock single-ended P signal. |
| Tx_HS_enable_C | Output | Signal to enable HS mode clock lane. |
| Tx_HS_C [7:0] | Output | HS mode differential clock bus. |
| Tx_LP_D_P [NUM_DATA_LANE-1:0] | Output | LP mode TX data single-ended P signal. |
| Tx_LP_D_N [NUM_DATA_LANE-1:0] | Output | LP mode TX data single-ended N signal. |
| Tx_LP_D_P_OE [NUM_DATA_LANE-1:0] | Output | Output enable for LP mode TX data single-ended P signal. |
| Tx_LP_D_N_OE [NUM_DATA_LANE-1:0] | Output | Output enable for LP mode TX data single-ended N signal. |
| Tx_HS_D_0[7:0] | Output | HS mode differential lane 0 data bus. |
| Tx_HS_D_1[7:0] | Output | HS mode differential lane 1 data bus. |
| Tx_HS_D_2[7:0] | Output | HS mode differential lane 2 data bus. |
| Tx_HS_D_3[7:0] | Output | HS mode differential lane 3 data bus. |
| Tx_HS_D_4[7:0] | Output | HS mode differential lane 4 data bus. |
| Tx_HS_D_5[7:0] | Output | HS mode differential lane 5 data bus. |
| Tx_HS_D_6[7:0] | Output | HS mode differential lane 6 data bus. |
| Tx_HS_D_7[7:0] | Output | HS mode differential lane 7 data bus. |
| Tx_HS_enable_D [NUM_DATA_LANE-1:0] | Output | Signal to enable HS mode data lane. |
| Rx_LP_D_P | Input | LP mode RX data single-ended P signal for bidirectional data lane. |
| Rx_LP_D_N | Input | LP mode RX data single-ended N signal for bidirectional data lane. |
| Port | Direction | Description |
|---|---|---|
| TxRequestHS [NUM_DATA_LANE-1:0] | Input |
HS Transmit Request and Data Valid.
A low-to-high transition causes the lane module to initiate a
start-of-transmission sequence. A high-to-low transition on causes
the lane module to initiate an end-of-transmission sequence.
This active-high signal also indicates that the protocol is driving
valid data on TxDataHS to be transmitted.
|
| TxDataHS_0 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxDataHS_1 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxDataHS_2 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxDataHS_3 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxDataHS_4 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxDataHS_5 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxDataHS_6 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxDataHS_7 [7:0] | Input | HS Transmit Data Bus. HS data to be transmitted. |
| TxSkewCalHS1 [NUM_DATA_LANE-1:0] | Input | HS Transmit Skew Calibration. This is an optional signal to
initiate the periodic deskew burst at the transmitter. A
low-to-high transition causes the PHY to initiate the transmission
of a skew calibration pattern. A high-to-low transition causes the
PHY to end the transmission of a skew calibration pattern, and
initiate an end-of-transmission sequence. |
| TxReadyHS [NUM_DATA_LANE-1:0] | Output | HS Transmit Ready. This active-high signal indicates that
TxDataHS is accepted by the lane module to be serially
transmitted. |
| TxTriggerEsc [3:0] | Input | Escape Mode Receive Trigger. These active high signals indicate
that a trigger event has been received. The asserted TxTriggerEsc
signal remains active until a stop state is detected on the lane
interconnect. Applicable to bidirectional mode
only. TxTriggerEsc[0] corresponds to
reset-trigger. TxTriggerEsc[1] corresponds to entry
sequence for HS test mode trigger. TxTriggerEsc[2]
corresponds to unknown-4 trigger. TxTriggerEsc[3]
corresponds to unknown-5 trigger. |
| TxRequestEsc [NUM_DATA_LANE-1:0] | Input | Escape Mode Transmit Request. This active-high signal is used to
request escape sequences. |
| TxStopStateD [NUM_DATA_LANE-1:0] | Output | Lane in Stop State. This active-high signal indicates that the
lane module is in stop state. |
| TxUlpsExit [NUM_DATA_LANE-1:0] | Input | Transmit ULPS Exit Sequence. This active-high signal is asserted
when ULPS is active and the protocol is ready to leave
ULPS. |
| TxUlpsActiveNot [NUM_DATA_LANE-1:0] | Output | ULPS (not) Active. This active-low signal is asserted to indicate
that the lane is in ULPS. |
| TxUlpsEsc [NUM_DATA_LANE-1:0] | Input | Escape Mode Transmit ULPS. This active-high signal is asserted
with TxRequestEsc to cause the lane module to enter the
ULPS. |
| TxLpdtEsc [NUM_DATA_LANE-1:0] | Input | Escape Mode Transmit LP Data. This active-high signal is asserted
with TxRequestEsc to cause the lane module to enter LP data
transmission mode. |
| TxValidEsc [NUM_DATA_LANE-1:0] | Input | Escape Mode Transmit Data Valid. This active-high signal
indicates that the protocol is driving valid data on TxDataEsc to be
transmitted. |
| TxDataEsc_0 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_0[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxDataEsc_1 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_1[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxDataEsc_2 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_2[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxDataEsc_3 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_3[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxDataEsc_4 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_4[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxDataEsc_5 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_5[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxDataEsc_6 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_6[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxDataEsc_7 [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc_7[0] is transmitted first. Data is captured on rising
edges of clk. |
| TxReadyEsc [NUM_DATA_LANE-1:0] | Output | Escape Mode Transmit Ready. This active-high signal indicates
that TxDataEsc is accepted bythe lane module to be serially
transmitted. TxReadyEsc is valid on rising edges of
TxClkEsc. |
| TxRequestHSc | Input |
HS Transmit Request and Data Valid.
A low-to-high transition causes the lane module to initiate a
start-of-transmission sequence. A high-to-low transition causes the
lane module to initiate an end-of-transmission sequence.
This active-high signal causes the lane module to begin
transmitting a HS clock.
|
| TxReadyHSc | Output | HS Transmit Ready. This active-high signal indicates that the
lane is transmitting a HS clock. |
| TxUlpsClk | Input | Transmit ULPS on Clock Lane. This active-high signal is asserted
to cause a Clock lane module to enter the ULPS. |
| TxUlpsExitClk | Input | Transmit ULPS Exit Sequence. This active-high signal is asserted
when ULPS is active and the protocol is ready to leave
ULPS. |
| TxUlpsActiveClkNot | Output | ULPS (not) Active. This active-low signal is asserted to indicate
that the lane is in ULPS. |
| TxStopStateC | Output | Lane in Stop state. This active-high signal indicates that the
lane module is in stop state. |
| TurnRequest | Input | Turnaround Request. This active high signal is used to indicate
that the protocol desires to initiate a bidirectional data lane
turnaround, to allow the other side to begin transmissions.
TurnRequest is valid on rising edge of clk. TurnRequest is only
meaningful for a bidirectional data lane module that is currently
the transmitter (Direction=0). If the bidirectional data lane module
is in receive mode (Direction=1), this signal is ignored. A
low-to-high transition on TurnRequest can only happen when Stopstate
is asserted. |
| TurnRequest_done | Output | Indicates that the RX D-PHY acknowledges the bus turnaround or timeout. If this signal is high together with turnaround timeout, it indicates that there is no acknowledgement from the RX on the turnaround request. |
| Turnaround_timeout | Output | Indicates that there is no acknowledgement from the RX D-PHY for the turnaround request and TX D-PHY ends the turnaround request. |
| RxUlpsEsc | Output | Escape ULPS. This active-high signal is asserted to indicate that
the lane module has entered the ULPS, due to the detection of a
received ULPS command. This signal is used only in Bidir data lane
mode. |
| RxUlpsActiveNot | Output | ULPS (not) Active. This active-low signal is asserted to indicate
that the lane is in ULPS. This signal is used only in bidirectional
data lane mode. |
| RxLPDTEsc | Output | Escape LP Data Receive Mode. This active-high signal is asserted
to indicate that the lane module is in LP data receive mode. This
signal is used only in bidirectional data lane mode. |
| RxValidEsc | Output | Escape LP Data Receive Mode. This active-high signal is asserted
to indicate that the lane module is in LP data receive mode. This
signal is used only in bidirectional data lane mode. |
| RxStopState | Output | Lane in Stop State. This active-high signal indicates that the
lane module is currently in stop state. This signal is used only in
bidirectional data lane mode. |
| RxDataEsc [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc[0] was received first. Data is transferred on rising edges
of clk. This signal is used only in bidirectional data lane
mode. |
| RxTriggerEsc [3:0] | Output | Escape Mode Receive Trigger. These active high signals indicate
that a trigger event has been received. The asserted RxTriggerEsc
signal remains active until a stop state is detected on the lane
interconnect. Applicable to bidirectional mode
only. RxTriggerEsc[0] corresponds to
reset-trigger. RxTriggerEsc[1] corresponds to entry
sequence for HS test mode trigger. RxTriggerEsc[2]
corresponds to unknown-4 trigger. RxTriggerEsc[3]
corresponds to unknown-5 trigger. |
| ErrEsc | Output | Escape Entry Error. If an unrecognized escape entry command is
received in LP mode, this active-high signal is asserted and remains
asserted until the next transaction starts, so that the protocol can
properly process the error. Applicable to bidirectional
mode only. |
| ErrControl | Output | Control Error. This active-high signal is asserted when an
incorrect line state sequence is detected in LP and ALP modes. Once
asserted, this signal remains asserted until the next transaction
starts, so that the protocol can properly process the
error. Applicable to bidirectional mode
only. |
1 HS Transmit Skew Calibration is not supported in
v2021.1EA.