Features

  • 1, 2, 4, or 8 configurable data lanes
  • Unidirectional (CSI) and bidirectional (DSI) data lane
  • High-speed (HS) mode for data communication and low-power (LP) mode for data communication
  • 100 MHz core clock frequency
  • HS byte clock frequency from 10 MHz up to 187 MHz (from 80 Mbps up to 1,500 Mbps data rate)1
  • Continuous HS byte clock and discontinuous HS byte clock
  • Supports 8 bits HS data width
  • Supports D-PHY-only, D-PHY with CSI, or D-PHY with DSI
  • Supports PHY protocol interface (PPI)
  • Supports end-of-transmission error, start-of-transmission sync error, control error, and LP escape error
1 The maximum data rate of IP depends on the devices. Refer to the respective device data sheet for more accurate information.