JTAG to SPI Flash Bridge Testbench

You can choose to generate the testbench when generating the core in the IP Manager Configuration window. To generate testbench, the Testbench Deliverables Option signals must be enabled.

Note: You must include all .v files generated in the /Testbench directory in your simulation.

Important: tested the testbench generated with the default parameter options only.

provides a simulation script for you to run the testbench quickly using the Modelsim software. To run the Modelsim testbench script, run vsim -do modelsim.do in a terminal application. You must have Modelsim installed on your computer to use this script.

There is a Python script, generate_tb_config.py, which generates testbench configuration and initialization file for the SPI flash. You need to run it by entering the command python3 generate_tb_config.py before starting the simulation.

The testbench performs several iterations of write and read tests. The written data to the flash loader is then compared with the data read from the flash memory. Additionally, it indicates an overall pass or fail for the entire test.

After running the simulation, the test prints the following message:

# SUCCESS: on-chip CRC test passed
# INFO: chip reset
# JEDEC ID manufacturer ID: ef
# JEDEC ID memory type: 70
# JEDEC ID capacity: 19
# SUCCESS: SPI Flash Read/Write test passed
# SUCCESS: flash_0 test passed
# INFO: chip reset
# JEDEC ID manufacturer ID: ef
# JEDEC ID memory type: 70
# JEDEC ID capacity: 19
# SUCCESS: SPI Flash Read/Write test passed
# SUCCESS: flash_1 test passed
# SUCCESS: all tests passed