IP Manager

The Efinity® IP Manager is an interactive wizard that helps you customize and generate Efinix® IP cores. The IP Manager performs validation checks on the parameters you set to ensure that your selections are valid. When you generate the IP core, you can optionally generate an example design targeting an Efinix development board and/or a testbench. This wizard is helpful when you use several IP cores, multiple instances of an IP core with different parameters, or the same IP core across different projects.

Note: Not all Efinix IP cores include an example design or a testbench.

Generating the JTAG to SPI Flash Bridge Core with the IP Manager

The following steps explain how to customize an IP core with the IP Configuration wizard.
  1. Open the IP Catalog.
  2. Choose Memory Controllers > JTAG to SPI Flash Bridge core and click Next. The IP Configuration wizard opens.
  3. Enter the module name in the Module Name box.
    Note: You cannot generate the core without a module name.
  4. (Optional) In the Deliverables tab, specify whether to generate an IP core example design targeting an Efinix® development board and/or testbench. These options are turned on by default.
    Note: You can migrate the provided example designs to quickly create a JTAG to SPI Flash Bridge for your own board. See for more information.
  5. (Optional) In the Summary tab, review your selections.
  6. Click Generate to generate the IP core and other selected deliverables.
  7. In the Review configuration generation dialog box, click Generate. The Console in the Summary tab shows the generation status.
    Note: You can disable the Review configuration generation dialog box by turning off the Show Confirmation Box option in the wizard.
  8. When generation finishes, the wizard displays the Generation Success dialog box. Click OK to close the wizard.

The wizard adds the IP to your project and displays it under IP in the Project pane.

Generated Files

The IP Manager generates these files and directories:
  • <module name>_tmpl.sv—Verilog HDL instantiation template.
  • <module name>_tmpl.vhd—VHDL instantiation template.
  • <module name>.sv—IP source code.
  • settings.json—Configuration file.
  • <kit name>_devkit—Has generated RTL, example design, and Efinity® project targeting a specific development board.
  • Testbench—Contains generated RTL and testbench files.