Using the JTAG to SPI Flash Bridge Core with Your Board
You can use the Trion® T120 BGA324 Development Board example design as a starting point if you have a Trion FPGA on your board. Then, migrate the design as your targeted FPGA.
Notice: Refer to the
Trion Hardware Design Checklist and Guidelines page of the Support Center,
Titanium Hardware Design Checklist and Guidelines page of the Support Center, or
Topaz Hardware Design Checklist and Guidelines page of the Support Center
for the SPI Active configuration pin circuitries.
Check the following settings before compiling the JTAG to SPI Flash Bridge example design.
Note: In addition to these settings, you need to verify whether Efinix supports your flash device. See Verified Flash Devices.
Dual Flash Support
If you have dual flash on your board, you need to select the SPI Active x8 using JTAG Bridge option when programming your board using the Efinity Programmer.
SPI Flash Resource Assignments
You need to verify the SPI flash resource assignments as follows:
| SPI Flash Pin | Trion Resource | Titanium/Topaz Resource |
|---|---|---|
| Flash#1 and #2 CLK | spi_clk | spi_clk |
| Flash#1 CS | spi0_cs | spi0_cs |
| Flash#1 IO0 (MOSI) | spi0_io[0] | spi0_io[0] |
| Flash#1 IO1 (MISO) | spi0_io[1] | spi0_io[1] |
| Flash#1 IO2 (WP#) | spi0_io[2] 1 | spi0_io[2] 1 |
| Flash#1 IO3 (HOLD#/RESET#) | spi0_io[3] 1 | spi0_io[3] 1 |
| Flash#2 CS | – | spi1_cs 2 |
| Flash#2 IO0 (MOSI) | – | spi1_io[0] 2 |
| Flash#2 IO1 (MISO) | – | spi1_io[1] 2 |
| Flash#2 IO2 (WP#) | – | spi1_io[2] 1 2 |
| Flash#2 IO3 (HOLD#/RESET#) | – | spi1_io[3] 1 2 |
Notice: Refer to the device Pinouts for the actual pin
names.
1 Leave unconnected if
there is no connection between the FPGA
and SPI flash.
2 Only required when using
the SPI Active x8 in JTAG Bridge programming mode.