Resource Utilization and Performance
Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
| FPGA | Logic Elements (Logic, Adders, Flipflops, etc.) | Memory Block | DSP Block | fMAX (MHz)1 | Efinity® Version2 |
|---|---|---|---|---|---|
| Ti60 F225 C4 | 1,145/60,800 (1.9%) | 0/256 (0%) | 0/160 (0%) | 168 | 2025.1 |
| Ti180 J484 C4 | 1,145/172,800 (0.7%) | 0/1,280 (0%) | 0/640 (0%) | 139 | 2025.1 |
| Ti375 C529 C4 | 1,145/362,880 (0.3%) | 0/2,688 (0%) | 0/1,344 (0%) | 135 | 2025.1 |
| Ti375 N1156 C4 | 1,145/362,880 (0.3%) | 0/2,688 (0%) | 0/1,344 (0%) | 135 | 2025.1 |
| FPGA | Logic Elements (Logic, Adders, Flipflops, etc.) | Memory Block | Multiplier Block | fMAX (MHz)1 | Efinity® Version2 |
|---|---|---|---|---|---|
| T120 F324 C4 | 1,048/112,128 (0.9%) | 0/1,056 (0%) | 0/320 (0%) | 73 | 2025.1 |
1 Using default parameter
settings.
2 Using
Verilog HDL.