Ti375 Revision History

Table 1. Revision History
Date Version Description
February 2026 2.0 Corrected packages in Table 20 and Table 21. (DOC-2877)
Corrected AXI interrupt signal direction in Hardened RISC-V Block Diagram. (DOC-2885)
Added pull-down resistor to HVIO figure Figure 1. (DOC-2884)
Added transceiver analog power supply (VDDA_H_Q) specification. (DOC-2910)
Corrected Figure 1 and Figure 5; they incorrectly showed two PLLs. (DOC-2932)
December 2025
1.9
 Updated DSP block diagram; W register moved to after adder. (DOC-2592)
Q3 speed grade added in tables. (DOC-2737)
Updated Table 2.
Updated Table 6. (DOC-2803)
Note added regarding reconfiguration to Ti375 Internal Reconfiguration Block.
Corrected definition for MIPI D-PHY signal ERR_SOT_HS_LANn; SOT is start of transmission. (DOC-2755)
The Efinity software issues a warning (not error) if you do not leave enough separation between GPIO and LVDS or MIPI lane pins (see note). (DOC-2833)
October 2025
1.8
 Added notes for Ti375 Single-Event Upset Detection. (DOC-2602)
Reduced minimum PMA Direct data rate. (DOC-2601)
Added note referring customer to AN 063 for PMA Direct Rx insertion loss guidelines. (DOC-2655)
Updated Figure 4; some N signals were incorrectly labeled as P. (DOC-2676)
June 2025
1.7
Added Ti375 Transceiver Specifications topic. (DOC-2282)
Updated PLL maximum locked time Table 2 (DOC-2468)
March 2025
1.6
Added N900 package information. (DOC-2366)
Updated configuration timing and fuse programming waveforms. (DOC-2272)
Moved table describing connection requirements for unused resources and features to the Ti375 Unused Resources and Features topic.
Updated differential I/O programmable delay chain step size specification. (DOC-2351)
Updated regional clock network figures to show that GPIOB_PN_01, GPIOB_PN_05, and GPIOB_PN_12 are MIPI RX clocks. (DOC-2389)
Corrected resource names in PLL reference clock resource assignments tables.
In Table 2, updated "When Configured As" column for Sub-LVDS and SLVS. (DOC-2314)
Added RISC-V memory clock speed to ref_dc_switch_ti60.html#ref_dc_switch_t20__table_q3p_jsj_hsb. (DOC-2278)
Added DLYCLK GPIO signal. (DOC-2159)
Updated GPIO and LVDS interface pin names (IN to I and OUT to O) to align with primitives. (DOC-2086)
Removed PLL IOFBK interface pin.
The SAMPLE/PRELOAD instruction is available after JTAG fuses have been blown. (DOC-2225)
N484 package now supports PCIe Gen 4. (DOC-2240)
October 2024
1.5
Fixed typo in Table 2. (DOC-2038)
Changed column name from Pins to Configuration Functions in Table 2. (DOC-2038)
Added note after Table 2 directing the reader to the device pinout file. (DOC-2038)
Updated Fuse Programming Requirements with details of VQPS current. (DOC-1999)
Clarified HVIO and HSIO pin states during configuration and when unused in user mode. (DOC-2041)
Added notes to the configuration timing and security feature topics about not using SPI and JTAG at the same time. (DOC-2047)
The transceiver supplies can be powered up in any sequence. (DOC-2131)
Updated configuration timing and fuse programming waveforns. (DOC-2156)
July 2024
1.4
 Added N484 package information.
Corrected resources for C529 package.
Corrected I/O banks for C529 and N1156 packages. (DOC-1959)
Added PLL reference clock resource assignments for N484 and N1156 packages. Corrected assignments for C529 package.
Removed duplicate FOUT specification in PLL Timing and AC Characteristics topic. (DOC-1947)
For I/O banks that do not have a VREF pin, the GPIO pins do not support the SSTL and HSTL input I/O standards. (DOC-1954)
Clarified which signals are available when LVDS settings are enabled. (DOC-1908)
Added missing DBG[5:0] signals to Table 2. (DOC-1908)
Added reset recommendations for PLLs and cascaded PLLs. (DOC-1900)
Revised presentation of data in Table 1 to improve clarity.
Updated specification for LPDDR4/4x DRAM interface maximum data rate for the N1156 package. (DOC-1804)
Updated tSU minimum value in Table 1 and tH minimum for Table 1. (DOC-1982)
If you are using transceivers, during power-up, the external reference clock must be ready before CRESET_N is released. (DOC-1985)
May 2024 1.3 Split specification for VCC18A_MIPI into VCC18A_MIPI_TX and VCC18A_MIPI_RX. (DOC-1895)
In fractional feedback mode, you cannot use the output from CLKOUT1 as a clock source for your design. (DOC-1882)
If you are not using a transceiver, its power pins can be left unconnected. (DOC-1877)
If you are not using the RISC-V block, the power pin can be left unconnected. (DOC-1899)
Added I4L speed grade to ref_dc_switch_ti60.html#ref_dc_switch_t20__table_q3p_jsj_hsb. (DOC-1804)
Added specification for LPDDR4/4x DRAM interface maximum data rate for the N1156 package. (DOC-1804)
March 2024 1.2 Updated oscillator specification. (DOC-1663)
Updated description for HSIO block DLY_INC signal. (DOC-1697)
Added note to Ti375 Power-Up Sequence about DDR DRAM power supply requirements. (DOC-1573)
Updated power ramp-up details in Ti375 Power-Up Sequence. (DOC-1683)
January 2024 1.1
Corrected OUTCLK connection in Figure 1. (DOC-1630)
Rearranged Ti375 Configuration Timing to keep waveforms together with tables.
Added specifications for 1.35 V.
Renamed SerDes as transceiver.
For the fractional PLL equation FVCO = (FPFD x M x O x CFBK ), removed the restriction that (M x O x CFBK) must be ≤ 255.
Modified setup time for passive mode x16 and x32.
December 2023
 1.0 Initial release.