Ti375 Features

  • High-density, low-power Quantum® compute fabric
  • Built on TSMC 16 nm process
  • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM
  • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting
  • Versatile on-chip clocking
    • Low-skew global network supporting 32 clock or control signals
    • Regional and local clock networks
    • Up to 12 PLLs with support for fractional-N division, programmable duty cycle, spread-spectrum clocking, and dynamic reconfiguration
  • FPGA interface blocks
    • 32-bit quad-core hardened RISC-V block
    • Four high-speed transceiver banks, each with 4 lanes:
      • Supports data rates from 1.25 Gbps up to 16 Gbps per channel
      • PCIe Gen4 x4:
        • Compliant with the PCIe® 4.0, 3.0, 2.1, and 1.1 specifications
        • Support x1, x2, and x4 configurations
        • Configure as Root Port (RP) or End Point (EP)
        • Single Root IO Virtualization (SRIOV)
      • Supports SGMII and 10GBase-KR protocols, as well as PMA Direct
    • Two LPDDR4/4x PHY interfaces (supporting x32 DQ widths) with memory controller hard IP
    • Three MIPI D-PHY RX and TX interfaces with speeds up to 2.5 Gbps
    • Two varieties of general-purpose I/O (GPIO) pins:
      • High-voltage I/O (HVIO) pins support 1.8, 2.5, and 3.3 V
      • Configurable high-speed I/O (HSIO) pins support
        • Single-ended and differential I/O
        • LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps
        • MIPI lane (DSI and CSI) in high-speed and low-power modes, up to 1.5 Gbps
    • One oscillator
    • Spread-Spectrum Clocking (SSC) PLL
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
    • Supports internal reconfiguration
  • Single-event upset (SEU) detection feature
  • N484 packages are available in an automotive (Q3) speed grade with
    • AEC-Q100 qualification
    • Production Part Approval Process (PPAP) documentation
  • Optional security feature
    • Asymmetric bitstream authentication using RSA-4096
    • Bitstream encryption/decryption using AES-GCM
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Important: All specifications are preliminary and pending hardware characterization.
Table 1. Ti375 FPGA Resources
Logic Elements (LEs) eXchangeable Logic and Routing (XLR) Cells Global Clock and Control Signals Embedded Memory (Mbits) Embedded Memory Blocks (10 Kbits) Embedded DSP Blocks
Total SRL81
370,137 362,880 67,200 Up to 32 27.53 2,688 1,344
Table 2. Ti375 Package-Dependent Resources
Resource N484 C529 N900 N1156
Single-ended GPIO (maximum) HVIO
LVCMOS: 1.8, 2.5, 3.0, 3.3 V
LVTTL: 3.0, 3.3 V
 20 51 50 103
HSIO
LVCMOS, HSTL: 1.2, 1.5, 1.8 V2
SSTL: 1.2, 1.35, 1.5, 1.8 V2
 85 176 168 234
Differential GPIO (maximum) HSIO (LVDS, Differential HSTL, and SSTL)2 42 88 84 117
HSIO (MIPI D-PHY Data Lanes) 28 64 66 100
HSIO (MIPI D-PHY Clock Lanes) 7 11 14 17
LPDDR4/4x PHY with memory controller 1 x32 1 x32 2 x32 2 x32
MIPI D-PHY Hard Blocks RX 1 – 2 3
TX or SSC PLL 1 – – 3
Global clock or control signals from GPIO pins 17 29 30 32
Fractional PLLs 9 12 12 12
Transceiver banks3 PCIe 1xGen4 – 2xGen4 2xGen4
SGMII, 10GBase-KR, or PMA Direct up to 2 – up to 4 up to 4
Note: The x32 LPDDR4/4x PHY with memory controller can be configured as x16 or x32 widths.
1 Number of XLR that can be configured as shift register with 8 maximum taps.
2 GPIOB_PN_00, GPIOB_PN_01, and GPIOB_PN_02 do not support the SSTL and HSTL input I/O standards.
3 Refer to Ti375 Transceiver Specifications for the data rates supported by different speed grade devices.