Efinix, Inc.
  • Ti240 Introduction
  • Ti240 Features
    • Ti240 Available Package Options
  • Ti240 Device Core Functional Description
    • Ti240 XLR Cell
    • Ti240 Embedded Memory
      • Ti240 True Dual-Port Mode
      • Ti240 Simple Dual-Port Mode
    • Ti240 DSP Block
    • Ti240 Clock and Control Network
      • Ti240 Clock Sources that Drive the Global and Regional Networks
      • Ti240 Driving the Global Network
      • Ti240 Driving the Regional Network
      • Ti240 Driving the Local Network
  • Ti240 Device Interface Functional Description
    • Ti240 Interface Block Connectivity
    • Ti240 GPIO
      • Ti240 Features for HVIO and HSIO Configured as GPIO
        • Ti240 Double-Data I/O
        • Ti240 Programmable Delay Chains
      • Ti240 HVIO
      • Ti240 HSIO
        • Ti240 HSIO Configured as GPIO
        • Ti240 HSIO Configured as LVDS
        • Ti240 HSIO Configured as MIPI Lane
      • Ti240 I/O Banks
    • Ti240 DDR DRAM Interface
    • Ti240 MIPI D-PHY
      • Ti240 MIPI RX D-PHY
      • Ti240 MIPI TX D-PHY
    • Ti240 Oscillator
    • Ti240 Fractional PLL
      • Ti240 Reference Clock Resource Assignments
      • Ti240 Programmable Duty Cycle
      • Ti240 Fractional Output Divider
      • Ti240 Spread-Spectrum Clocking
      • Ti240 Dynamic PLL Reconfiguration
      • Ti240 Dynamic Phase Shift
    • Ti240 Spread-Spectrum Clocking PLL
    • Ti240 Hardened RISC-V Block Interface
    • Ti240 Transceiver Interface
    • Ti240 Single-Event Upset Detection
    • Ti240 Internal Reconfiguration Block
  • Ti240 Security Feature
  • Ti240 Power Sequence
    • Ti240 Power-Up Sequence
    • Ti240 Power-Down Sequence
    • Ti240 Power Supply Current Transient
    • Ti240 Unused Resources and Features
  • Ti240 Configuration
    • Ti240 Supported Configuration Modes
  • Ti240 Characteristics and Timing
    • Ti240 DC and Switching Characteristics
    • Ti240 HSIO Electrical and Timing Specifications
    • Ti240 MIPI Electrical Specifications and Timing
      • Ti240 MIPI Reset Timing
    • Ti240 PLL Timing and AC Characteristics
    • Ti240 Configuration Timing
      • Ti240 JTAG Mode
      • Ti240 SPI Active Mode
      • Ti240 SPI Passive Mode
    • Ti240 Transceiver Specifications
  • Ti240 Pinout Description
    • Ti240 Configuration Pins
    • Ti240 Dedicated DDR Pinout
    • Ti240 Dedicated MIPI D-PHY Pinout
    • Ti240 Dedicated Transceiver Pinout
    • Ti240 Pin States
  • Ti240 Interface Floorplan
  • Ti240 Efinity Software Support
  • Ti240 Ordering Codes
  • Ti240 Revision History

Ti240 Characteristics and Timing

The following table shows the specification status for Ti240 packages.

Table 1. Package Status
Package Status
N484 Preliminary
C529 Preliminary
N900 Preliminary
N1156 Preliminary
  • Ti240 DC and Switching Characteristics
  • Ti240 HSIO Electrical and Timing Specifications
  • Ti240 MIPI Electrical Specifications and Timing
  • Ti240 PLL Timing and AC Characteristics
  • Ti240 Configuration Timing
  • Ti240 Transceiver Specifications

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