Ti240 MIPI RX D-PHY

The MIPI RX D-PHY is a receiver interface designed to receive data and the control information of MIPI CSI, DSI, or other associated protocols. The MIPI RX D-PHY comprises of one clock lane and up to four data lanes for a single-channel configuration. The MIPI RX D-PHY also interfaces with MIPI-associated protocol controllers via a standard MIPI D-PHY PHY Protocol Interface (PPI) that supports the 8- or 16-bit high-speed receiving data bus.

Figure 1. MIPI RX D-PHY x4 Block Diagram

The status signals provide optional status and error information about the MIPI RX D-PHY interface operation.

Figure 2. MIPI RX D-PHY Interface Block Diagram
Table 1. MIPI RX D-PHY Clocks Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
CFG_CLK Input N/A Configuration Clock (used for time counter and EQ calibration). The clock must be between 80 MHz to 120 MHz.
WORD_CLKOUT_HS Output N/A HS Receive Byte/Word clock.
LP_CLK Output N/A Low Power State clock.
RX_CLK_ESC_LANn Output N/A Escape Mode Receive clock.
TX_CLK_ESC Input N/A Escape Mode Transmit clock. The clock must be lower than 20 MHz.
Table 2. MIPI RX D-PHY Control and Status Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
RESET_N Input N/A Reset. Disables PHY and reset the digital logic.
RST0_N Input N/A Asynchronous FIFO reset and synchronous out of reset.
STOPSTATE_CLK Output N/A Lane in Stop State.
STOPSTATE_LANn Output N/A Data Lane in Stop State (Lane N).
ERR_ESC_LANn Output N/A Lane n Escape Command Error.
ERR_CONTROL_LANn Output N/A Lane n Has Line State Error.
TX_REQUEST_ESC Input TX_CLK_ESC Lane 0 Request TX Escape Mode.
TURN_REQUEST Input TX_CLK_ESC Lane 0 Request Turnaround.
FORCE_RX_MODE Input N/A Lane 0 Force Lane into Receive Mode/Wait for Stop State.
TX_TRIGGER_ESC [3:0] Input TX_CLK_ESC Lane 0 Send a Trigger Event.
RX_TRIGGER_ESC [3:0] Output RX_CLK_ESC_LAN0 Lane 0 Received a Trigger Event.
DIRECTION Output N/A Lane 0 Transmit/Receive Direction (0 = TX, 1 = RX).
ERR_CONTENTION_LP0 Output N/A Lane 0 Contention Error when driving 0.
ERR_CONTENTION_LP1 Output N/A Lane 0 Contention Error when driving 1.
Table 3. MIPI RX D-PHY High-Speed Mode Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
RX_CLK_ACTIVE_HS Output N/A HS Clock Lane Active.
RX_ACTIVE_HS_LANn Output WORD_CLKOUT_HS HS Reception Active.
RX_VALID_HS_LANn Output WORD_CLKOUT_HS HS Data Receive Valid.
RX_SYNC_HS_LANn Output WORD_CLKOUT_HS HS Reveiver Sync. Observed.
RX_SKEW_CAL_HS_LANn Output WORD_CLKOUT_HS HS Reveiver DeSkew Burst Received.
RX_DATA_HS_LANn [15:0] Output WORD_CLKOUT_HS HS Receive Data.
ERR_SOT_HS_LANn Output WORD_CLKOUT_HS Start-of-Transmission (SOT) Error.
ERR_SOT_SYNC_HS_LANn Output WORD_CLKOUT_HS SOT Sync. Error.
Table 4. MIPI RX D-PHY Low-Power Data Receive Mode Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
RX_LPDT_ESC Output RX_CLK_ESC_LAN0 Lane 0 enter LPDT RX Mode.
RX_DATA_ESC [7:0] Output RX_CLK_ESC_LAN0 Lane 0 LPDT RX Data.
RX_VALID_ESC Output RX_CLK_ESC_LAN0 Lane 0 LPDT RX Data Valid.
ERR_SYNC_ESC Output N/A Lane 0 LPDT RX Data Sync. Error.
TX_LPDT_ESC Input TX_CLK_ESC Lane 0 Enter LPDT TX Mode.
TX_DATA_ESC [7:0] Input TX_CLK_ESC Lane 0 LPDT TX Data.
TX_VALID_ESC Input TX_CLK_ESC Lane 0 LPDT TX Data Valid.
TX_READY_ESC Output TX_CLK_ESC Lane 0 LDPT TX Data Ready.
Table 5. MIPI RX D-PHY ULP Sleep Mode Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
TX_ULPS_ESC Input TX_CLK_ESC Lane 0 Enter ULPS Mode.
TX_ULPS_EXIT Input TX_CLK_ESC Lane 0 Exit ULPS Mode.
RX_ULPS_CLK_NOT Output N/A CLK0 Enter ULPS Mode.
RX_ULPS_ACTIVE_CLK_NOT Output N/A CLK0 is in ULPS (Active Low).
RX_ULPS_ESC_LANn Output RX_CLK_ESC_LANn Lane n Enter ULPS Mode.
RX_ULPS_ACTIVE_NOT_LANn Output N/A Lane n is in ULPS (Active Low).
Table 6. MIPI RX D-PHY Pads
Pad Direction Description
MIPIn_RXDP[4:0] Bidirectional MIPI transceiver P pads.
MIPIn_RXDN[4:0] Bidirectional MIPI transceiver N pads.