Ti240 Configuration
The Ti240 FPGA contains volatile Configuration RAM (CRAM). The user must configure the CRAM for the desired logic function upon power-up and before the FPGA enters normal operation. The FPGA's control block manages the configuration process and uses a bitstream to program the CRAM. The Efinity® software generates the bitstream, which is design dependent. You can configure the Ti240 FPGA(s) in SPI active, SPI passive, or JTAG mode.
In active mode, the FPGA controls the configuration
process. The configuration clock can either be provided by an oscillator circuit
within the FPGA or an external clock connected to the
EXT_CONFIG_CLK pin. The bitstream is typically stored in an
external serial flash device, which provides the bitstream when the FPGA requests
it.
The control block sends out the instruction and address to read the configuration data. First, it issues a release from power-down instruction to wake up the external SPI flash. Then, it waits for at least 30 μs before issuing a fast read command to read the content of SPI flash from address 24h’000000 for 3-byte addressing mode or 32'h00000000 for 4-byte addressing mode.
In passive mode, the FPGA is the slave and relies on an
external master to provide the control, bitstream, and clock for configuration.
Typically the master is a microcontroller or another FPGA in active mode. The controller must wait for at least 32 μs after
CRESET is de-asserted before it can send the bitstream.
In JTAG mode, you configure the FPGA via the JTAG interface.
JTAG_VCCIO_SEL pin that selects
the voltage to use for JTAG. Refer to Ti240 Pinout Description for
more details.