T8 Revision History

Updated CBSEL[1:0] in Table 3.

Updated configuration timing waveforms. (DOC-2325)

Moved information about unused resources to T8 Unused Resources and Features.

Fixed typo in Table 3. (DOC-2038)

Added note about external DC-biased circuit is required if the incoming LVDS signals are AC-coupled and link to Trion Hardware Design Checklist and Guidelines. (DOC-1532)

Added LVDS RX Static Mode Delay Setting. (DOC-1473)

Updated Maximum Toggle Rate table by adding recommendation to run simulation for actual toggle rate. (DOC-1468)

Updated 2.5 V and 1.8 LVCMOS Single-Ended I/O Internal Weak Pull-Up and Pull-Down Resistance. (DOC-1476)

Updated maximum LVDS toggle rate for Q144 package. (DOC-1441)

Removed t_{LVDS_DT} and t_INDT specs, and replaced with t_{PLL_HLW} and t_{LVDS_CPA} for Q144 packages. (DOC-1189)

Updated PLL LOCKED signal description. (DOC-1208)

Corrected t_{LVDS_SU} and t_{LVDS_HD} specs (DOC-1070)

Updated Advanced PLL RSTN signal description about de-asserting only when CLKIN is stable. (DOC-1226)

Updated t_{LVDS_skew} specs. (DOC-1111)

Updated t_{LVDS_SU} specs (DOC-1070)

Updated power up sequence diagram. (DOC-954)

Added note to use LVDS blocks from the same side to minimize skew. (DOC-1150)

Updated Advanced PLL Settings table descriptions. (DOC-945)

Added note recommending up to only 2 cascading advanced PLLs. (DOC-931)

Corrected I_OH and I_OL in buffer drive strength characteristic specifications. (DOC-933)

Updated F_VCO, F_PLL, and F_PFD Advanced PLL Timing parameter specifications and PLL Interface Designer Settings - Manual Configuration Tab notes. (DOC-1019)

Added tLVDS_SU, tLVDS_HD specs and LVDS RX timing waveforms.

Removed PLL_EXTFB from alternative input. (DOC-849)

Updated Advanced PLL LOCKED signal description. (DOC-763)

Updated test condition load to maximum load in Maximum Toggle Rate Table. (DOC-781)

Updated note about leaving at least 2 pairs of unassigned LVDS pins between any GPIO and LVDS in the same device side. (DOC-769)

Updated supported maximum VCO frequency to 1,200 MHz for F49 and F81 packages. (DOC-722)

Updated behaviour description for GPIO and LVDS as GPIO pins during configuration, and unused GPIO pins during user mode. (DOC-720)

Added note about the block RAM content is random and undefined if it is not initialized. (DOC-729)

Updated power supply ramp rate and power up sequence diagram. (DOC-631)

Added Output Differential Voltage with Reduce VOD Swing option enabled specs. (DOC-648)

Added maximum I/O pin input current, I_IN, and maximum per bank specs. (DOC-652)

Added PLL input clock duty cycle, t_INDT, specs. (DOC-661)

Updated CDONE pin direction as bidirectional. (DOC-672)

Added storage temperature, T_STG spec. (DOC-560)

Updated maximum JTAG mode TCK frequency, f_TCK. (DOC-574)

Updated CSI pin description. (DOC-546)

Updated LVDS Pins Configured as Single-Ended I/O Buffer Drive Strength specifications. (DOC-578)

Update LVDS standard compliance which is TIA/EIA-644. (DOC-592)

Updated t_CLKH and t_CLKL, and corrected SPI Passive Mode (x1) Timing Sequence waveform. (DOC-590)

Updated REF_RES_xx description. (DOC-602, DOC-605)

Updated Maximum Toggle Rate table. (DOC-630)

Updated minimum Power Supply Ramp Rates. (DOC-631)

Added note to Active mode configuration clock frequency stating that for parallel daisy chain x2 and x4 configuration, f_{MAX_M}, must be set to DIV4. (DOC-528)

Added Global Clock Location topic. (DOC-532)

Added Maximum t_USER for SPI Active and Passive Modes topic. (DOC-535)

Added internal weak pull-up and pull-down resistor specs. (DOC-485)

Updated table title for Single-Ended I/O Schmitt Trigger Buffer Characteristic. (DOC-507)

Added note in Pinout Description stating all dedicated configuration pins have Schmitt Trigger buffer. (DOC-507)

Updated CRESET_N pin description. (DOC-450)

Added note about limiting number of LVDS as GPIO output and bidirectional per I/O bank to avoid switching noise. (DOC-411)

Added LVDS TX data and timing relationship waveform. (DOC-359)

Added LVDS RX I/O electrical specification waveform. (DOC-346)

Added data for C4L and I4L DC speed grades. (DOC-268)

Updated Advanced PLL reference clock input note by asking reader to refer to PLL Timing and AC Characteristics (Q144). (DOC-336)

Added other PLL input clock frequency sources in PLL Timing and AC Characteristics (Q144). (DOC-336)

Removed OE and RST from LVDS block as they are not supported in software. (DOC-328)

Added a table to Power Up Sequence topic describing pin connection when PLL or GPIO is not used. (DOC-325)

Updated f_{MAX_S} for passive configuration modes. (DOC-350)

Removed typical standby (low power [LP] option) from static supply current table and updated typical standby value for F49 and F81 packages.

Updated t_USER timing parameter values and added a note about the conditions for the values.

Updated description for GPIO pins state during configuration to exclude LVDS as GPIO.

Added operating junction temperature for industrial speed grade for F49 and F81 packages.

Updated block RAM and multiplier block maximum frequencies to include I2 speed grade.

Added f_MAX for single-ended I/O and LVDS configured as single-ended I/O.

Added maximum power supply current transient during power-up.

Removed preliminary note from F_OUT, F_VCO, t_DT, and t_OPJIT. These specifications are final.

Updated timing parameter symbols in boundary scan timing waveform to reflect JTAG mode parameter symbols.

Added supported GPIO features.

Updated the maximum F_VCO for advanced PLL to 1,600 MHz.

Updated the C divider requirement for the 90 degrees phase shift in the Advanced PLL Interface Designer Settings - Manual Configuration Tab.

Removed LVDS electrical specifications note about RX differential I/O standard support. Added as a note in LVDS functional description topic.

Added note to LVDS RX interface block diagram.

Updated I/O bank names from TL_CORNER, BL_CORNER, TR_CORNER, and BR_CORNER to TL, BL, TR, and BR respectively.

Updated the term DSP to multiplier.

Updated power up sequence description about holding CRESET_N low.

Updated PLLCLK pin name to PLL_CLKIN.

Added PLL_EXTFB as an alternative input in GPIO signals table for complex I/O buffer.

Updated PLL names in PLL reference clock resource assignments.

Added Trion power-up sequence.

Updated number of global clocks and controls that can come from GPIO pins in package resources table.

Removed DIV1 and DIV2 active mode configuration frequencies; they are not supported.

Added note to LVDS electrical specifications about RX differential I/O standard support.

Updated the reference clock pin assignments for TL_PLL0 and TL_PLL1.

Added waveforms for configuration timing.

Added packaging and floorplan information.

Updated configuration timing and PLL timing information.

Updated configuration pin table.

Updated ordering codes.

Clarified the slew rate description.