Efinix, Inc.
  • T8 Introduction
  • T8 Features
    • T8 Available Package Options
  • T8 Device Core Functional Description
    • T8 XLR Cell
    • T8 Logic Cell
    • T8 Embedded Memory
    • T8 Multipliers
    • T8 Global Clock Network
      • T8 Clock and Control Distribution Network
      • T8 Global Clock Location (Q144)
  • T8 Device Interface Functional Description
    • T8 Interface Block Connectivity
    • T8 General-Purpose I/O Logic and Buffer
    • T8 I/O Banks
    • T8 F49 and F81 Interface Description
      • T8 Simple I/O Buffer
      • T8 Simple PLL
      • T8 Oscillator
    • T8 Q144 Interface Description
      • T8 Complex I/O Buffer
        • T8 Double-Data I/O
      • T8 Advanced PLL
      • T8 LVDS
        • T8 LVDS TX
        • T8 LVDS RX
  • T8 Power Up Sequence
    • T8 Power Supply Current Transient
    • T8 Unused Resources and Features
  • T8 Configuration
    • T8 Supported Configuration Modes
    • T8 Mask-Programmable Memory Option
  • T8 DC and Switching Characteristics (F49 and F81)
  • T8 DC and Switching Characteristics (Q144)
  • T8 LVDS I/O Electrical and Timing Specifications (Q144)
  • T8 ESD Performance
  • T8 PLL Timing and AC Characteristics (F49 and F81)
  • T8 PLL Timing and AC Characteristics (Q144)
  • T8 Internal Oscillator (F49 and F81)
  • T8 Configuration Timing
    • T8 SPI Active
    • T8 SPI Passive
    • T8 JTAG
    • T8 Maximum tUSER for SPI Active and Passive Modes
  • T8 Pinout Description
    • T8 Pin States
  • T8 Efinity Software Support
  • T8 Interface Floorplan
  • T8 Ordering Codes
  • T8 Revision History

T8 Q144 Interface Description

T8 FPGAs in Q144 packages have advanced general-purpose I/O logic and buffers, I/O banks, advanced PLLs, and supports LVDS interface.

  • T8 Complex I/O Buffer
  • T8 Advanced PLL
  • T8 LVDS
Parent topic: T8 Device Interface Functional Description

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