T8 Configuration Timing

The T8 FPGA has the following configuration timing specifications. Refer to AN 006: Configuring Trion FPGAs for detailed configuration information.

Table 1. Timing Parameters for All Modes
Symbol Parameter Min Typ Max Units
tCRESET_N Minimum creset_n low pulse width required to trigger re-configuration. 320 – – ns
tUSER Minimum configuration duration after CDONE goes high before entering user mode.12
Test condition at 10 kΩ pull-up resistance and 10 pF output loading on CDONE pin.
 12 – 3 μs
1 The FPGA may go into user mode before tUSER has elapsed. However, Efinix recommends that you keep the system interface to the FPGA in reset until tUSER has elapsed.
2 For JTAG programming, the min tUSER configuration time is required after CDONE goes high and FPGA receives the ENTERUSER instruction from JTAG host (TAP controller in UPDATE_IR state).
3 See T8 Maximum tUSER for SPI Active and Passive Modes