T8 Power Up Sequence

Efinix® recommends the following power up sequence when powering Trion® FPGAs:

Figure 1. Trion® FPGAs Power Up Sequence
  1. Power up VCC and VCCA_xx first.
  2. When VCC and VCCA_xx are stable, power up all VCCIO pins. There is no specific timing delay between the VCCIO pins.
    Important: Ensure the power ramp rate is within VCCIO/10 V/ms to 10 V/ms.
  3. After all power supplies are stable, hold CRESET_N low for a duration of tCRESET_N before asserting CRESET_N from low to high to trigger active SPI programming (the FPGA loads the configuration data from an external flash device).
  4. FPGA configuration can begin after there has been a tDMIN minimum delay after CRESET_N goes high (see T8 SPI Passive and T8 JTAG for the delay specification).

When you are not using the GPIO or PLL resources, connect the pins as shown in the following table.

Note: Refer to T8 Configuration Timing for timing information.