T8 Features

  • High-density, low-power Quantum® architecture
  • Built on SMIC 40 nm process
  • Less than 150 μA typical core leakage current at 1.1 V1
  • Ultra-small footprint package options
  • FPGA interface blocks
    • GPIO
    • PLL
    • LVDS 600 Mbps per lane with up to 6 TX pairs and 6 RX pairs2
    • Oscillator
  • Programmable high-performance I/O
    • Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces3
  • Flexible on-chip clocking
    • 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals
    • PLL support
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
    • Optional Mask Programmable Memory (MPM) capability
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1. T8 FPGA Resources
LEs4 Dedicated Global Clocks Dedicated Global Controls Embedded Memory (kbits) Embedded Memory Blocks (5 Kbits) Embedded Multipliers
7,384 Up to 16 Up to 8 122.88 24 8
Table 2. T8 FPGA Package-Dependent Resources
Resource F49 F81 Q144
Available GPIO5 33 55 97
Global clocks from GPIO pins 4 8 6
Global controls from GPIO pins 5 8 8
PLL (simple) 1 1 –
PLL (advanced) – – 5
Oscillator 1 1 –
MPM 1 (optional) 1 (optional) 1 (optional)
LVDS – – 6 TX pairs
6 RX pairs
Notice: Refer to the Trion Packaging User Guide for the package outlines and markings.
1 F49 and F81 packages only.
2 LVDS pins are only available in Q144 packages.
3 LVDS pins used as GPIO only support 3.3 V.
4 Logic capacity in equivalent LE counts.
5 The LVDS I/O pins are dual-purpose. The full number of GPIO are available when all LVDS I/O pins are in GPIO mode. GPIO and LVDS as GPIO supports different features. See Table 2.