T55 Global Clock Location

The following tables describe the location of the global clock signals in T55 FPGAs.

Table 1. Left Clock Input from GPIO Pins

Function Name	Resource Name	GCLK[0]	GCLK[1]	GCLK[2]	GCLK[3]	GCLK[4]	GCLK[5]	GCLK[6]	GCLK[7]
CLK0	GPIOL_66		–	–	–		–	–	–
CLK1	GPIOL_67	–		–	–	–		–	–
CLK2	GPIOL_68	–	–		–	–	–		–
CLK3	GPIOL_69	–	–	–		–	–	–
CLK4	GPIOL_70		–	–	–		–	–	–
CLK5	GPIOL_71	–		–	–	–		–	–
CLK6	GPIOL_72	–	–		–	–	–		–
CLK7	GPIOL_73	–	–	–		–	–	–

Table 2. Left Clock from PLL OUTCLK Signal

PLL Reference	CLKOUT	GCLK[0]	GCLK[1]	GCLK[2]	GCLK[3]	GCLK[4]	GCLK[5]	GCLK[6]	GCLK[7]
PLL_TL0	CLKOUT0		–	–	–	–			–
	CLKOUT1	–		–		–	–	–
	CLKOUT2	–	–		–		–	–	–
PLL_BL0	CLKOUT0		–	–		–	–	–
	CLKOUT1	–		–	–		–		–
	CLKOUT2	–	–		–	–		–	–

Table 3. Right Clock Input from GPIO Pins

Function Name	Resource Name	GCLK[8]	GCLK[9]	GCLK[10]	GCLK[11]	GCLK[12]	GCLK[13]	GCLK[14]	GCLK[15]
CLK0	GPIOR_181		–	–	–	–	–	–	–
CLK1	GPIOR_180	–		–	–	–	–	–	–
CLK2	GPIOR_179	–	–		–	–	–	–	–
CLK3	GPIOR_178	–	–	–		–	–	–	–
CLK4	GPIOR_177	–	–	–	–		–	–	–
CLK5	GPIOR_176	–	–	–	–	–		–	–
CLK6	GPIOR_175	–	–	–	–	–	–		–
CLK7	GPIOR_174	–	–	–	–	–	–	–

Table 4. Right Clock from PLL OUTCLK Signal

PLL Reference	CLKOUT	GCLK[8]	GCLK[9]	GCLK[10]	GCLK[11]	GCLK[12]	GCLK[13]	GCLK[14]	GCLK[15]
PLL_TR0	CLKOUT0		–	–	–	–	–		–
	CLKOUT1	–			–	–	–	–	–
	CLKOUT2	–			–	–	–	–	–
PLL_TR1	CLKOUT0		–	–		–	–	–	–
	CLKOUT1	–	–	–	–			–	–
	CLKOUT2	–	–	–	–			–	–
PLL_TR2	CLKOUT0		–	–	–	–	–	–
	CLKOUT1	–			–	–	–	–	–
	CLKOUT2	–			–	–	–	–	–
PLL_BR0	CLKOUT0	–	–	–		–	–	–
	CLKOUT1	–	–	–	–			–	–
	CLKOUT2	–	–	–	–			–	–
PLL_BR1	CLKOUT0	–	–		–	–	–		–
	CLKOUT1	–	–	–			–	–	–
	CLKOUT2	–	–	–			–	–	–
PLL_BR2	CLKOUT0	–	–	–	–	–		–	–
	CLKOUT1	–		–	–	–	–		–
	CLKOUT2	–	–	–	–	–	–	–