T55 Interface Floorplan

Note: The numbers in the floorplan figures indicate the GPIO and LVDS number ranges. Some packages may not have all GPIO or LVDS pins in the range bonded out. Refer to the T55 Pinout for information on which pins are available in each package.
Figure 1. Floorplan Diagram for F324 Packages (with DDR and MIPI)

Figure 2. Floorplan Diagram for F484 Packages (with DDR)

Figure 3. Floorplan Diagram for F576 Packages (with DDR and MIPI)