Efinix, Inc.
  • T55 Introduction
  • T55 Features
    • T55 Available Package Options
  • T55 Device Core Functional Description
    • T55 XLR Cell
    • T55 Logic Cell
    • T55 Embedded Memory
    • T55 Multipliers
    • T55 Global Clock Network
      • T55 Clock and Control Distribution Network
      • T55 Global Clock Location
  • T55 Device Interface Functional Description
    • T55 Interface Block Connectivity
    • T55 General-Purpose I/O Logic and Buffer
      • T55 Complex I/O Buffer
      • T55 Double-Data I/O
    • T55 I/O Banks
    • T55 PLL
    • T55 LVDS
      • T55 LVDS TX
      • T55 LVDS RX
    • T55 MIPI
      • T55 MIPI TX
        • T55 MIPI TX Video Data TYPE[5:0] Settings
      • T55 MIPI RX
        • T55 MIPI RX Video Data TYPE[5:0] Settings
      • T55 D-PHY Timing Parameters
    • T55 DDR DRAM
      • T55 DDR Interface Designer Settings
  • T55 Power Up Sequence
    • T55 Power Supply Current Transient
    • T55 Unused Resources and Features
  • T55 Configuration
    • T55 Supported Configuration Modes
  • T55 DC and Switching Characteristics
  • T55 LVDS I/O Electrical and Timing Specifications
  • T55 ESD Performance
  • T55 MIPI Electrical Specifications and Timing
    • T55 MIPI Power-Up Timing
    • T55 MIPI Reset Timing
  • T55 PLL Timing and AC Characteristics
  • T55 Configuration Timing
    • T55 SPI Active
    • T55 SPI Passive
    • T55 JTAG
    • T55 Maximum tUSER for SPI Active and Passive Modes
  • T55 Pinout Description
    • T55 Pin States
  • T55 Efinity Software Support
  • T55 Interface Floorplan
  • T55 Ordering Codes
  • T55 Revision History

T55 ESD Performance

Refer to the Trion Reliability Report for ESD performance data.

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