T55 Features

  • High-density, low-power Quantum® architecture
  • Built on SMIC 40 nm process
  • FPGA interface blocks
    • GPIO
    • PLL
    • LVDS 800 Mbps per lane with up to 52 TX pairs and 52 RX pairs
    • MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane
    • DDR3, DDR3L, LPDDR3, LPDDR2 x32 PHY (supporting x16 or x32 DQ widths) with memory controller hard IP, up to 1066 Mbps
  • Programmable high-performance I/O
    • Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces
  • Flexible on-chip clocking
    • 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals
    • PLL support
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1. Resources
LEs1 Global Clock Networks Global Control Networks Embedded Memory (kbits) Embedded Memory Blocks ( Kbits) Embedded Multipliers
Up to 16 Up to
Table 2. T55 Package-Dependent Resources
Resource F324 F484 F576
Available GPIO2 130 256 278
Global clocks from GPIO pins 5 16 14
Global controls from GPIO pins 5 16 14
PLLs 7 8 8
LVDS 20 TX pairs
26 RX pairs
 40 TX pairs
40 RX pairs
 52 TX pairs
52 RX pairs
MIPI DPHY with CSI-2 controller
(4 data lanes, 1 clock lane)
 2 TX blocks
2 RX blocks
– 3 TX blocks
3 RX blocks
DDR3, DDR3L, LPDDR3, LPDDR2 PHY with memory controller 1 block (x16 DQ widths) 1 block (x16 or x32 DQ widths) 1 block (x16 or x32 DQ widths)
Notice: Refer to the Trion Packaging User Guide for the package outlines and markings.
1 Logic capacity in equivalent LE counts.
2 The LVDS I/O pins are dual-purpose. The full number of GPIO are available when all LVDS I/O pins are in GPIO mode. GPIO and LVDS as GPIO supports different features. See Table 2.