T4 Pin States
GPIO pins have as internal pull up/down (see Figure 1). The following table shows the pin state during reset, configuration, and when unused in user mode.
| Pin Type | During Reset (CRESET_N Low) |
During Configuration (CRESET_N High, CDONE Low) |
When Unused in User Mode (Default) |
|---|---|---|---|
| User Pins | |||
| GPIO | Input tri-state with weak pull up. | Input tri-state with weak pull up. | Input tri-state with weak pull up.1 |
| LVDS used as GPIO | Input tri-state with no weak pull up or pull down. | Input tri-state with no weak pull up or pull down. | Input tri-state with weak pull up. |
| Dual-Purpose Configuration Pins | |||
| CSO | 0 | 02 | Input tri-state with weak pull up. |
| NSTATUS | 1 | 13 | Input tri-state with weak pull up. |
| CCK | Input tri-state with weak pull up. | SPI active output clock. SPI passive input with weak pull up. | Input tri-state with weak pull up. |
| CDI0 | Input tri-state with weak pull up. | SPI active output. SPI passive input with weak pull up. | Input tri-state with weak pull up. |
As shown in T4 Power Up Sequence, CRESET_N must be
kept low during power up.
Note: Refer to the following tables for details:
1 You can change it to weak
pull-down in the Interface Designer.
2 CSO is driven to 1 when the bitstream is done transmitting
(CDONE = 1).
3 NSTATUS is
driven to 0 if the FPGA detects an invalid
bitstream (e.g., CRC error).