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T4 Introduction
T4 Features
T4 Available Package Options
T4 Device Core Functional Description
T4 XLR Cell
T4 Logic Cell
T4 Embedded Memory
T4 Multipliers
T4 Global Clock Network
T4 Clock and Control Distribution Network
T4 Device Interface Functional Description
T4 Interface Block Connectivity
T4 General-Purpose I/O Logic and Buffer
T4 Simple I/O Buffer
T4 I/O Banks
T4 PLL
T4 Oscillator
T4 Power Up Sequence
T4 Power Supply Current Transient
T4 Unused Resources and Features
T4 Configuration
T4 Supported Configuration Modes
T4 Mask-Programmable Memory Option
T4 DC and Switching Characteristics
T4 ESD Performance
T4 PLL Timing and AC Characteristics
T4 Internal Oscillator
T4 Configuration Timing
T4 SPI Active
T4 SPI Passive
T4 JTAG
T4 Maximum tUSER for SPI Active and Passive Modes
T4 Pinout Description
T4 Pin States
T4 Efinity Software Support
T4 Interface Floorplan
T4 Ordering Codes
T4 Revision History
T4
ESD Performance
Refer to the
Trion Reliability Report
for ESD performance data.