The following tables describe the PLL timing and AC characteristics.
Table 1. PLL Timing
| Symbol |
Parameter |
Min |
Typ |
Max |
Units |
| FPFD |
Phase frequency detector input frequency. |
10 |
– |
50 |
MHz |
| FOUT |
Output clock frequency. |
0.25 |
– |
400 |
MHz |
| FVCO |
PLL VCO frequency. |
500 |
– |
1200 |
MHz |
Table 2. PLL AC Characteristics
| Symbol |
Parameter |
Min |
Typ |
Max |
Units |
| tDT |
Output clock duty cycle. |
40 |
50 |
60 |
% |
| tOPJIT (PK - PK) |
Output clock period jitter (PK-PK). |
– |
100 |
– |
ps |
| tINDT |
Input clock duty cycle. |
45 |
– |
55 |
% |
| tILJIT (PK - PK) |
Input clock long-term jitter (PK-PK) |
– |
– |
800 |
ps |
| tLOCK |
PLL pull in plus lock-in time. |
– |
– |
0.5 |
ms |