T4 Revision History

Updated CBSEL[1:0] in Table 3.

Updated configuration timing waveforms. (DOC-2325)

Moved information about unused resources to T4 Unused Resources and Features.

Fixed typo in Table 3. (DOC-2038)

Footnote added to Table 1. (DOC-1939)

Added Pin States topic. (DOC-2087)

SPI and JTAG pins should not be active at the same time for configuration. (DOC-2046)

Renamed package prefix to match Efinity software (e.g., BGA changesd to F).

Added note about external DC-biased circuit is required if the incoming LVDS signals are AC-coupled and link to Trion Hardware Design Checklist and Guidelines. (DOC-1532)

Updated Maximum Toggle Rate table by adding recommendation to run simulation for actual toggle rate. (DOC-1468)

Updated 2.5 V and 1.8 LVCMOS Single-Ended I/O Internal Weak Pull-Up and Pull-Down Resistance. (DOC-1476)

Updated power up sequence diagram. (DOC-954)

Updated test condition load to maximum load in Maximum Toggle Rate Table. (DOC-781)

Updated supported maximum VCO frequency to 1,200 MHz. (DOC-722)

Updated behaviour description for unused GPIO pins during user mode. (DOC-720)

Added note about the block RAM content is random and undefined if it is not initialized. (DOC-729)

Updated power supply ramp rate and power up sequence diagram. (DOC-631)

Added maximum I/O pin input current, I_IN, and maximum per bank specs. (DOC-652)

Added PLL input clock duty cycle, t_INDT, specs. (DOC-661)

Updated CDONE pin direction as bidirectional. (DOC-672)

Added storage temperature, T_STG spec. (DOC-560)

Updated maximum JTAG mode TCK frequency, f_TCK. (DOC-574)

Updated CSI pin description. (DOC-546)

Updated t_CLKH and t_CLKL, and corrected SPI Passive Mode (x1) Timing Sequence waveform. (DOC-590)

Updated minimum Power Supply Ramp Rates. (DOC-631)

Updated Maximum Toggle Rate table. (DOC-630)

Added note to Active mode configuration clock frequency stating that for parallel daisy chain x2 and x4 configuration, f_{MAX_M}, must be set to DIV4. (DOC-528)

Added Maximum t_USER for SPI Active and Passive Modes topic. (DOC-535)

Added internal weak pull-up and pull-down resistor specs. (DOC-485)

Added note in Pinout Description stating all dedicated configuration pins have Schmitt Trigger buffer. (DOC-507)

Updated table title for Single-Ended I/O Schmitt Trigger Buffer Characteristic. (DOC-507)

Updated CRESET_N pin description. (DOC-450)

Added a table to Power Up Sequence topic describing pin connection when PLL or GPIO is not used. (DOC-325)

Updated f_{MAX_S} for passive configuration modes. (DOC-350)

Updated t_USER timing parameter values and added a note about the conditions for the values.

Updated description for GPIO pins state during configuration.

Added operating junction temperature for industrial speed grade.

Updated block RAM and multiplier block maximum frequencies to include I2 speed grade.

Added maximum power supply current transient during power-up.

Updated timing parameter symbols in boundary scan timing waveform to reflect JTAG mode parameter symbols.

Added supported GPIO features.

Updated power up sequence description about holding CRESET_N low.

Updated PLLCLK pin name to PLL_CLKIN.

Added Trion power-up sequence.

Updated number of global clocks and controls that can come from GPIO pins in package resources table.

Removed DIV1 and DIV2 active mode configuration frequencies; they are not supported.

Added waveforms for configuration timing.

Minor formatting changes.

Added floorplan information.

Updated configuraiton timing and PLL timing information.

Renamed RST PLL pin as RSTN.

Updated ordering codes.