T4 Features

  • High-density, low-power Quantum® architecture
  • Built on SMIC 40 nm process
  • Less than 150 μA typical core leakage current at 1.1 V
  • Ultra-small footprint package options
  • FPGA interface blocks
    • GPIO
    • PLL
    • Oscillator
  • Programmable high-performance I/O
    • Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces
  • Flexible on-chip clocking
    • 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals
    • PLL support
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
    • Optional Mask Programmable Memory (MPM) capability
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1. T4 FPGA Resources
LEs1 Global Clock Networks Global Control Networks Embedded Memory (kbits) Embedded Memory Blocks (5 Kbits) Embedded Multipliers
3,888 Up to 16 Up to 8 76.8 15 4
Table 2. T4 FPGA Package-Dependent Resources
Resource F49 F81
Available GPIO 33 55
Global clocks from GPIO pins 4 8
Global controls from GPIO pins 5 8
PLL (simple) 1 1
Oscillator 1 1
MPM 1 (optional) 1 (optional)
Notice: Refer to the Trion Packaging User Guide for the package outlines and markings.
1 Logic capacity in equivalent LE counts.