Introduction

Resetting a DDR block involves more than a simple reset; you also need to reconfigure the block and re-initialize the memory. The DDR Hard Memory Controller-Reset core manages this process for you. The DDR Hard Memory Controller-Reset core resets and re-initializes the Trion FPGA's DDR interface as well as the DDR module(s). You use this soft logic reset when you want to reset the DDR system while the FPGA is in user mode.

Use the IP Manager to select IP, customize it, and generate files. The DDR Hard Memory Controller-Reset core has an interactive wizard to help you set parameters. The wizard also has options to create a testbench and/or example design targeting an Efinix® development board.