Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.
Table 2. Trion Resource Utilization and Performance
FPGA Logic Utilizations (LUTs) Registers Memory Blocks Multipliers fMAX (MHz)1 Efinity® Version2
T20 BGA256 C4 34 26 0 0 234 2021.1
1 Using default parameter settings.
2 Using Verilog HDL.