Ports

Table 1. DDR Hard Memory Controller-Reset Core Ports

Port	Direction	Description
ddr_rstn_i	Input	Master asynchronous reset.
clk	Input	User clock.
ddr_rstn	Output	Active-low master DDR reset. Requires re-configuration and initialization after de-assertion. Connect to DDR interface block.
ddr_cfg_seq_rst	Output	Active-high DDR configuration controller reset. Connect to DDR interface block.
ddr_cfg_seq_start	Output	Start the DDR configuration controller. Connect to DDR interface block.
dr_init_done	Output	Optional status monitor for user logic. Goes high when reconfiguration and re-initialization is complete.